Gerald E. Sobelman

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Hanho Lee

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Publications

2011
[j15]
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Sangmin Kim, Gerald E. Sobelman, Hanho Lee:
A Reduced-Complexity Architecture for LDPC Layered Decoding Schemes. IEEE Trans. Very Large Scale Integr. Syst. 19(6): 1099-1103 (2011)
[c56]
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Kyung-Il Baek, Hanho Lee, Chang-Seok Choi, Sangmin Kim, Gerald E. Sobelman:
A high-throughput LDPC decoder architecture for high-rate WPAN systems. ISCAS 2011: 1311-1314
2008
[c48]
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Sangmin Kim, Gerald E. Sobelman, Hanho Lee:
Flexible LDPC decoder architecture for high-throughput applications. APCCAS 2008: 45-48
[c44]
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Sangmin Kim, Gerald E. Sobelman, Hanho Lee:
Adaptive quantization in min-sum based irregular LDPC decoder. ISCAS 2008: 536-539
2004
[j9]
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Hanho Lee, Gerald E. Sobelman:
VLSI Design Of Digit-Serial FPGA Architecture. J. Circuits Syst. Comput. 13(1): 17-52 (2004)
2003
[j8]
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Hanho Lee, Gerald E. Sobelman:
Performance evaluation and optimal design for FPGA-based digit-serial DSP functions. Comput. Electr. Eng. 29(2): 357-377 (2003)
1999
[c14]
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Lijun Gao, Sarvesh Shrivastava, Hanho Lee, Gerald E. Sobelman:
A Compact Fast Variable Key Size Elliptic Curve Cryptosystem Coprocessor. FCCM 1999: 304-305
1998
[c13]
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Hanho Lee, Gerald E. Sobelman:
Digit-Serial DSP Library for Optimized FPGA Configuration. FCCM 1998: 322-323
[c12]
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Hanho Lee, Sarvesh Shrivastava, Gerald E. Sobelman:
FPGA Logic Block Architecture for Digit-Serial DSP Applications (Abstract). FPGA 1998: 257
1997
[c11]
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Hanho Lee, Gerald E. Sobelman:
A New Low-Voltage Full Adder Circuit. Great Lakes Symposium on VLSI 1997: 88-

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