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ORCIDTorsten Hoefler
- > Home > Persons > Torsten Hoefler
Publications
- 2024
[j62]Thomas Benz
, Michael Rogenmoser, Paul Scheffler, Samuel Riedel, Alessandro Ottaviano, Andreas Kurth, Torsten Hoefler, Luca Benini:
A High-Performance, Energy-Efficient Modular DMA Engine Architecture. IEEE Trans. Computers 73(1): 263-277 (2024)- [c274]Samuel Riedel, Marc Gantenbein, Alessandro Ottaviano, Torsten Hoefler, Luca Benini:
LRSCwait: Enabling Scalable and Efficient Synchronization in Manycore Systems Through Polling-Free and Retry-Free Operation. DATE 2024: 1-6 - [c262]Mikhail Khalilov, Marcin Chrapek, Siyuan Shen, Alessandro Vezzu, Thomas Benz, Salvatore Di Girolamo, Timo Schneider, Daniele De Sensi, Luca Benini, Torsten Hoefler:
OSMOSIS: Enabling Multi-Tenancy in Datacenter SmartNICs. USENIX ATC 2024: 247-263 - [i175]Samuel Riedel, Marc Gantenbein, Alessandro Ottaviano, Torsten Hoefler, Luca Benini:
LRSCwait: Enabling Scalable and Efficient Synchronization in Manycore Systems through Polling-Free and Retry-Free Operation. CoRR abs/2401.09359 (2024) - 2023
- [j55]Paul Scheffler, Florian Zaruba, Fabian Schuiki, Torsten Hoefler, Luca Benini:
Sparse Stream Semantic Registers: A Lightweight ISA Extension Accelerating General Sparse Linear Algebra. IEEE Trans. Parallel Distributed Syst. 34(12): 3147-3161 (2023) - [c258]Patrick Iff, Maciej Besta, Matheus A. Cavalcante, Tim Fischer, Luca Benini, Torsten Hoefler:
Sparse Hamming Graph: A Customizable Network-on-Chip Topology. DAC 2023: 1-6 - [c257]Patrick Iff, Maciej Besta, Matheus A. Cavalcante, Tim Fischer, Luca Benini, Torsten Hoefler:
HexaMesh: Scaling to Hundreds of Chiplets with an Optimized Chiplet Arrangement. DAC 2023: 1-6 - [i147]Thomas Benz, Michael Rogenmoser, Paul Scheffler, Samuel Riedel, Alessandro Ottaviano, Andreas Kurth, Torsten Hoefler, Luca Benini:
A High-performance, Energy-efficient Modular DMA Engine Architecture. CoRR abs/2305.05240 (2023) - [i146]Paul Scheffler, Florian Zaruba, Fabian Schuiki, Torsten Hoefler, Luca Benini:
Sparse Stream Semantic Registers: A Lightweight ISA Extension Accelerating General Sparse Linear Algebra. CoRR abs/2305.05559 (2023) - [i133]Mikhail Khalilov, Marcin Chrapek, Siyuan Shen, Alessandro Vezzu, Thomas Benz, Salvatore Di Girolamo, Timo Schneider, Daniele De Sensi, Luca Benini, Torsten Hoefler:
OSMOSIS: Enabling Multi-Tenancy in Datacenter SmartNICs. CoRR abs/2309.03628 (2023) - [i126]Patrick Iff, Benigna Bruggmann, Maciej Besta, Luca Benini, Torsten Hoefler:
RapidChiplet: A Toolchain for Rapid Design Space Exploration of Chiplet Architectures. CoRR abs/2311.06081 (2023) - 2022
- [c235]Andrea Cossettini, Konstantin Taranov, Christian Vogt, Michele Magno, Torsten Hoefler, Luca Benini:
A RDMA Interface for Ultra-Fast Ultrasound Data-Streaming over an Optical Link. DATE 2022: 80-83 - [i98]Patrick Iff, Maciej Besta, Matheus A. Cavalcante, Tim Fischer, Luca Benini, Torsten Hoefler:
Sparse Hamming Graph: A Customizable Network-on-Chip Topology. CoRR abs/2211.13980 (2022) - [i97]Patrick Iff, Maciej Besta, Matheus A. Cavalcante, Tim Fischer, Luca Benini, Torsten Hoefler:
HexaMesh: Scaling to Hundreds of Chiplets with an Optimized Chiplet Arrangement. CoRR abs/2211.13989 (2022) - 2021
- [j44]Fabian Schuiki, Florian Zaruba, Torsten Hoefler, Luca Benini:
Stream Semantic Registers: A Lightweight RISC-V ISA Extension Achieving Full Compute Utilization in Single-Issue Cores. IEEE Trans. Computers 70(2): 212-227 (2021) - [j43]Florian Zaruba, Fabian Schuiki, Torsten Hoefler, Luca Benini:
Snitch: A Tiny Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloads. IEEE Trans. Computers 70(11): 1845-1860 (2021) - [c204]Paul Scheffler, Florian Zaruba, Fabian Schuiki, Torsten Hoefler, Luca Benini:
Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra. DATE 2021: 1787-1792 - [c200]Salvatore Di Girolamo, Andreas Kurth, Alexandru Calotoiu, Thomas Benz, Timo Schneider, Jakub Beránek, Luca Benini, Torsten Hoefler:
A RISC-V in-network accelerator for flexible high-performance low-power packet processing. ISCA 2021: 958-971 - 2020
- [c181]Andreas Kurth, Samuel Riedel, Florian Zaruba, Torsten Hoefler, Luca Benini:
ATUNs: Modular and Scalable Support for Atomic Operations in a Shared Memory Multiprocessor. DAC 2020: 1-6 - [i73]Florian Zaruba, Fabian Schuiki, Torsten Hoefler, Luca Benini:
Snitch: A 10 kGE Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloads. CoRR abs/2002.10143 (2020) - [i60]Salvatore Di Girolamo, Andreas Kurth, Alexandru Calotoiu, Thomas Benz, Timo Schneider, Jakub Beránek, Luca Benini, Torsten Hoefler:
PsPIN: A high-performance low-power architecture for flexible in-network compute. CoRR abs/2010.03536 (2020) - [i46]Paul Scheffler, Florian Zaruba, Fabian Schuiki, Torsten Hoefler, Luca Benini:
Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra. CoRR abs/2011.08070 (2020) - 2019
- [c150]Salvatore Di Girolamo, Konstantin Taranov, Andreas Kurth, Michael Schaffner, Timo Schneider, Jakub Beránek, Maciej Besta, Luca Benini, Duncan Roweth, Torsten Hoefler:
Network-accelerated non-contiguous memory transfers. SC 2019: 56:1-56:14 - [i34]Salvatore Di Girolamo, Konstantin Taranov, Andreas Kurth, Michael Schaffner, Timo Schneider, Jakub Beránek, Maciej Besta, Luca Benini, Duncan Roweth, Torsten Hoefler:
Network-Accelerated Non-Contiguous Memory Transfers. CoRR abs/1908.08590 (2019) - [i24]Fabian Schuiki, Florian Zaruba, Torsten Hoefler, Luca Benini:
Stream Semantic Registers: A Lightweight RISC-V ISA Extension Achieving Full Compute Utilization in Single-Issue Cores. CoRR abs/1911.08356 (2019)
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