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Publications
- 2012
[j55]Naga Sasidhar, David Gubbins, Pavan Kumar Hanumolu, Un-Ku Moon:
Rail-to-Rail Input Pipelined ADC Incorporating Multistage Signal Mapping. IEEE Trans. Circuits Syst. II Express Briefs 59-II(9): 558-562 (2012)- [c87]Pavan Kumar Hanumolu, Un-Ku Moon, Terri S. Fiez:
Tutorial T5: Advanced Analog-Mixed Signal System and Circuit Techniques. VLSI Design 2012: 20-21 - 2011
- [j52]Igor Vytyaz, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram:
Design-Oriented Analysis of Circuits With Equality Constraints. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(5): 1089-1098 (2011) - 2010
- [j47]David Gubbins, Bumha Lee, Pavan Kumar Hanumolu, Un-Ku Moon:
Continuous-Time Input Pipeline ADCs. IEEE J. Solid State Circuits 45(8): 1456-1468 (2010) - 2009
- [j44]Ting Wu, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon:
Method for a Constant Loop Bandwidth in LC-VCO PLL Frequency Synthesizers. IEEE J. Solid State Circuits 44(2): 427-435 (2009) - [j41]Min-Gyu Kim, Pavan Kumar Hanumolu, Un-Ku Moon:
A 10 MS/s 11-bit 0.19 mm2 Algorithmic ADC With Improved Clocking Scheme. IEEE J. Solid State Circuits 44(9): 2348-2355 (2009) - [j40]Naga Sasidhar, Youn-Jae Kook, Seiji Takeuchi, Koichi Hamashita, Kaoru Takasuka, Pavan Kumar Hanumolu, Un-Ku Moon:
A Low Power Pipelined ADC Using Capacitor and Opamp Sharing Technique With a Scheme to Cancel the Effect of Signal Dependent Kickback. IEEE J. Solid State Circuits 44(9): 2392-2401 (2009) - [j39]Igor Vytyaz, David C. Lee, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram:
Automated Design and Optimization of Low-Noise Oscillators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(5): 609-622 (2009) - [j36]Volodymyr Kratyuk, Pavan Kumar Hanumolu, Kerem Ok, Un-Ku Moon, Kartikeya Mayaram:
A Digital PLL With a Stochastic Time-to-Digital Converter. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(8): 1612-1621 (2009) - [c72]Sunwoo Kwon, Pavan Kumar Hanumolu, Sang-Ho Kim, Sung-No Lee, Seung-Bin You, Ho-Jin Park, Jae-Whui Kim, Un-Ku Moon:
An 11mW 100MHz 16X-OSR 64dB-SNDR hybrid CT/DT ΔΣ ADC with relaxed DEM timing. CICC 2009: 171-174 - [c71]David Gubbins, Sunwoo Kwon, Bumha Lee, Pavan Kumar Hanumolu, Un-Ku Moon:
A continuous-time input pipeline ADC with inherent anti-alias filtering. CICC 2009: 275-278 - [c70]Skyler Weaver, Benjamin P. Hershberg, Pavan Kumar Hanumolu, Un-Ku Moon:
A multiplexer-based digital passive linear counter (PLINCO). ICECS 2009: 607-610 - 2008
- [j35]Pavan Kumar Hanumolu, Volodymyr Kratyuk, Gu-Yeon Wei, Un-Ku Moon:
A Sub-Picosecond Resolution 0.5-1.5 GHz Digital-to-Phase Converter. IEEE J. Solid State Circuits 43(2): 414-424 (2008) - [j34]Pavan Kumar Hanumolu, Gu-Yeon Wei, Un-Ku Moon:
A Wide-Tracking Range Clock and Data Recovery Circuit. IEEE J. Solid State Circuits 43(2): 425-439 (2008) - [j33]Min-Gyu Kim, Gil-Cho Ahn, Pavan Kumar Hanumolu, Sanghyeon Lee, Sang-Ho Kim, Seung-Bin You, Jae-Whui Kim, Gabor C. Temes, Un-Ku Moon:
A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC. IEEE J. Solid State Circuits 43(5): 1195-1206 (2008) - [j31]Igor Vytyaz, David C. Lee, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram:
Sensitivity Analysis for Oscillators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(9): 1521-1534 (2008) - [c68]David Gubbins, Bumha Lee, Pavan Kumar Hanumolu, Un-Ku Moon:
A continuous-time input pipeline ADC. CICC 2008: 169-172 - [c67]Igor Vytyaz, Josh Carnes, Ting Wu, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram:
Noise tolerant oscillator design using perturbation projection vector analysis. CICC 2008: 695-698 - [c66]Peter Kurahashi, Pavan Kumar Hanumolu, Un-Ku Moon:
A 1V downconversion filter using duty-cycle controlled bandwidth tuning. CICC 2008: 707-710 - [c65]Igor Vytyaz, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram:
Periodic Steady-State Analysis Augmented with Design Equality Constraints. DATE 2008: 312-317 - 2007
- [j28]Peter Kurahashi, Pavan Kumar Hanumolu, Gabor C. Temes, Un-Ku Moon:
Design of Low-Voltage Highly Linear Switched-R-MOSFET-C Filters. IEEE J. Solid State Circuits 42(8): 1699-1709 (2007) - [j26]Volodymyr Kratyuk, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram:
A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy. IEEE Trans. Circuits Syst. II Express Briefs 54-II(3): 247-251 (2007) - [c59]Volodymyr Kratyuk, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon:
A 0.6GHz to 2GHz Digital PLL with Wide Tracking Range. CICC 2007: 305-308 - [c57]Gil-Cho Ahn, Min-Gyu Kim, Pavan Kumar Hanumolu, Un-Ku Moon:
A 1V 10b 30MSPS Switched-RC Pipelined ADC. CICC 2007: 325-328 - [c56]Merrick Brownlee, Pavan Kumar Hanumolu, Un-Ku Moon:
A 3.2Gb/s Oversampling CDR with Improved Jitter Tolerance. CICC 2007: 353-356 - [c55]Pavan Kumar Hanumolu, Gu-Yeon Wei, Un-Ku Moon, Kartikeya Mayaram:
Digitally-Enhanced Phase-Locking Circuits. CICC 2007: 361-368 - [c54]Ting Wu, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon:
A 4.2 GHz PLL Frequency Synthesizer with an Adaptively Tuned Coarse Loop. CICC 2007: 547-550 - [c52]Igor Vytyaz, David C. Lee, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram:
Sensitivity analysis for oscillators. ICCAD 2007: 458-463 - [c48]Josh Carnes, Igor Vytyaz, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon:
Design and Analysis of Noise Tolerant Ring Oscillators Using Maneatis Delay Cells. ICECS 2007: 494-497 - 2006
- [j24]Merrick Brownlee, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon:
A 0.5-GHz to 2.5-GHz PLL With Fully Differential Supply Regulated Tuning. IEEE J. Solid State Circuits 41(12): 2720-2728 (2006) - [c42]Pavan Kumar Hanumolu, Min-Gyu Kim, Gu-Yeon Wei, Un-Ku Moon:
A 1.6Gbps Digital Clock and Data Recovery Circuit. CICC 2006: 603-606 - [c41]Peter Kurahashi, Pavan Kumar Hanumolu, Gabor C. Temes, Un-Ku Moon:
A 0.6V Highly Linear Switched-R-MOSFET-C Filter. CICC 2006: 833-836 - [c39]Nasser Talebbeydokhti
, Pavan Kumar Hanumolu, Peter Kurahashi, Un-Ku Moon:
Constant transconductance bias circuit with an on-chip resistor. ISCAS 2006 - [c37]Merrick Brownlee, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon:
A 0.5 to 2.5GHz PLL with Fully Differential Supply-Regulated Tuning. ISSCC 2006: 2412-2421 - 2005
- [j21]Gowtham Vemulapalli, Pavan Kumar Hanumolu, Youn-Jae Kook, Un-Ku Moon:
A 0.8-V accurately tuned linear continuous-time filter. IEEE J. Solid State Circuits 40(9): 1972-1977 (2005) - [c35]Volodymyr Kratyuk, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram:
A low spur fractional-N frequency synthesizer architecture. ISCAS (3) 2005: 2807-2810 - [c34]Ting Wu, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram:
An FMDLL based dual-loop frequency synthesizer for 5 GHz WLAN applications. ISCAS (4) 2005: 3986-3989 - 2004
- [j12]Pavan Kumar Hanumolu, Merrick Brownlee, Kartikeya Mayaram, Un-Ku Moon:
Analysis of charge-pump phase-locked loops. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(9): 1665-1674 (2004) - [c30]Gowtham Vemulapalli, Pavan Kumar Hanumolu, Un-Ku Moon:
A 0.8V accurately-tuned continuous-time filter. CICC 2004: 45-48 - [c28]Pavan Kumar Hanumolu, Bryan Casper, Randy Mooney, Gu-Yeon Wei, Un-Ku Moon:
Jitter in high-speed serial and parallel links. ISCAS (4) 2004: 425-428 - 2003
- [j8]Pavan Kumar Hanumolu, Bryan Casper, Randy Mooney, Gu-Yeon Wei, Un-Ku Moon:
Analysis of PLL clock jitter in high-speed serial links. IEEE Trans. Circuits Syst. II Express Briefs 50(11): 879-886 (2003)
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