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ORCIDWei-Chung Hsu
- > Home > Persons > Wei-Chung Hsu
Publications
- 2019
[j28]Sheng-Yu Fu, Ding-Yong Hong
, Yu-Ping Liu, Jan-Jan Wu, Wei-Chung Hsu:
Optimizing data permutations in structured loads/stores translation and SIMD register mapping for a cross-ISA dynamic binary translator. J. Syst. Archit. 98: 173-190 (2019)- [j27]Ding-Yong Hong, Jan-Jan Wu, Yu-Ping Liu, Sheng-Yu Fu, Wei-Chung Hsu:
Processor-Tracing Guided Region Formation in Dynamic Binary Translation. ACM Trans. Archit. Code Optim. 15(4): 52:1-52:25 (2019) - [j26]Yu-Ping Liu, Ding-Yong Hong, Jan-Jan Wu, Sheng-Yu Fu, Wei-Chung Hsu:
Exploiting SIMD Asymmetry in ARM-to-x86 Dynamic Binary Translation. ACM Trans. Archit. Code Optim. 16(1): 2:1-2:24 (2019) - [c75]Sheng-Yu Fu, Wei-Chung Hsu:
Translating Traditional SIMD Instructions to Vector Length Agnostic Architectures. CGO 2019: 275 - [c74]Chih-Min Lin, Sheng-Yu Fu, Ding-Yong Hong, Yu-Ping Liu, Jan-Jan Wu, Wei-Chung Hsu:
Exploiting Vector Processing in Dynamic Binary Translation. ICPP 2019: 93:1-93:10 - [c73]Zi Xuan Huang, Sheng-Yu Fu, Wei-Chung Hsu:
Efficient Dynamic Device Placement for Deep Neural Network Training on Heterogeneous Systems. SAMOS 2019: 51-64 - 2018
- [j25]Sheng-Yu Fu, Ding-Yong Hong, Yu-Ping Liu, Jan-Jan Wu, Wei-Chung Hsu:
Efficient and retargetable SIMD translation in a dynamic binary translator. Softw. Pract. Exp. 48(6): 1312-1330 (2018) - [j24]Ding-Yong Hong, Yu-Ping Liu, Sheng-Yu Fu, Jan-Jan Wu, Wei-Chung Hsu:
Improving SIMD Parallelism via Dynamic Binary Translation. ACM Trans. Embed. Comput. Syst. 17(3): 61:1-61:27 (2018) - [c72]Sheng-Yu Fu, Chih-Min Lin, Ding-Yong Hong, Yu-Ping Liu, Jan-Jan Wu, Wei-Chung Hsu:
Exploiting SIMD capability in an ARMv7-to-ARMv8 dynamic binary translator. CASES 2018: 14:1-14:3 - [c71]Chih-Yung Liang, Sheng-Yu Fu, Yu-Ping Liu, Wei-Chung Hsu:
Automatically Migrating Sequential Applications to Heterogeneous System Architecture. HPCS 2018: 114-121 - [c70]Shih-Kai Lin, Ding-Yong Hong, Sheng-Yu Fu, Jan-Jan Wu, Wei-Chung Hsu:
Dynamic tuning of applications using restricted transactional memory. RACS 2018: 249-254 - 2017
- [c68]Yu-Ping Liu, Ding-Yong Hong, Jan-Jan Wu, Sheng-Yu Fu, Wei-Chung Hsu:
Exploiting Asymmetric SIMD Register Configurations in ARM-to-x86 Dynamic Binary Translation. PACT 2017: 343-355 - [c67]Sheng-Yu Fu, Ding-Yong Hong, Yu-Ping Liu, Jan-Jan Wu, Wei-Chung Hsu:
Dynamic translation of structured Loads/Stores and register mapping for architectures with SIMD extensions. LCTES 2017: 31-40 - [c65]Kuo-You Peng, Sheng-Yu Fu, Yu-Ping Liu, Wei-Chung Hsu:
Adaptive runtime exploiting sparsity in tensor of deep learning neural network on heterogeneous systems. SAMOS 2017: 105-112 - 2016
- [c62]Ding-Yong Hong, Sheng-Yu Fu, Yu-Ping Liu, Jan-Jan Wu, Wei-Chung Hsu:
Exploiting Longer SIMD Lanes in Dynamic Binary Translation. ICPADS 2016: 853-860 - 2015
- [c59]Sheng-Yu Fu, Jan-Jan Wu, Wei-Chung Hsu:
Improving SIMD code generation in QEMU. DATE 2015: 1233-1236 - [c57]Sheng-Yu Fu, Ding-Yong Hong, Jan-Jan Wu, Pangfeng Liu, Wei-Chung Hsu:
SIMD Code Translation in an Enhanced HQEMU. ICPADS 2015: 507-514
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