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ORCIDGörschwin Fey
- > Home > Persons > Görschwin Fey
Publications
- 2010
[j9]Stephan Eggersglüß, Görschwin Fey
, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Rolf Drechsler:
MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics. J. Electron. Test. 26(3): 307-322 (2010)- 2009
- [b4]Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille:
Test Pattern Generation using Boolean Proof Engines. Springer 2009, ISBN 978-90-481-2359-9, pp. I-XII, 1-192 - [j6]Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Jürgen Schlöffel, Daniel Tille:
Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern (Efficient Satisfiability Solving Algorithms for Test Pattern Generation). it Inf. Technol. 51(2): 102-111 (2009) - 2008
- [j3]Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Daniel Tille:
On Acceleration of SAT-Based ATPG for Industrial Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(7): 1329-1333 (2008) - [i1]Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille:
SAT-based Automatic Test Pattern Generation. Evolutionary Test Generation 2008 - 2007
- [c32]Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler:
SAT-based ATPG for Path Delay Faults in Sequential Circuits. ISCAS 2007: 3671-3674 - [c31]Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel:
Experimental Studies on SAT-Based ATPG for Gate Delay Faults. ISMVL 2007: 6 - [c30]Görschwin Fey, Daniel Große, Stephan Eggersglüß, Robert Wille, Rolf Drechsler:
Formal Verification on the Word Level using SAT-like Proof Techniques. MBMV 2007: 81-90 - [c28]Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel:
Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults. MEMOCODE 2007: 181-187 - [c27]Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler:
SWORD: A SAT like Prover Using Word Level Information. VLSI-SoC (Selected Papers) 2007: 1-17 - [c26]Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler:
SWORD: A SAT like prover using word level information. VLSI-SoC 2007: 88-93
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