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ORCIDBane Vasic
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Publications
- 2012
[j26]Dung Viet Nguyen, Shashi Kiran Chilappagari, Michael W. Marcellin, Bane Vasic:
On the Construction of Structured LDPC Codes Free of Small Trapping Sets. IEEE Trans. Inf. Theory 58(4): 2280-2302 (2012)- 2011
- [j25]Shashi Kiran Chilappagari, Michael Chertkov
, Bane Vasic:
An Efficient Instanton Search Algorithm for LP Decoding of LDPC Codes Over the BSC. IEEE Trans. Inf. Theory 57(7): 4417-4426 (2011) - 2010
- [j22]Shashi Kiran Chilappagari, Dung Viet Nguyen, Bane Vasic, Michael W. Marcellin:
On trapping sets and guaranteed error correction capability of LDPC codes and GLDPC codes. IEEE Trans. Inf. Theory 56(4): 1600-1611 (2010) - [j21]Shashi Kiran Chilappagari, Dung Viet Nguyen, Bane Vasic, Michael W. Marcellin:
Error correction capability of column-weight-three LDPC codes under the Gallager A algorithm-Part II. IEEE Trans. Inf. Theory 56(6): 2626-2639 (2010) - [c38]Shiva Kumar Planjery, David Declercq, Shashi Kiran Chilappagari, Bane Vasic:
Multilevel decoders surpassing belief propagation on the binary symmetric channel. ISIT 2010: 769-773 - [c37]Shashi Kiran Chilappagari, Michael Chertkov, Bane Vasic:
Worst configurations (instantons) for Compressed Sensing over reals: A channel coding approach. ISIT 2010: 1978-1982 - [c36]Shiva Kumar Planjery, Shashi Kiran Chilappagari, Bane Vasic, David Declercq, Ludovic Danjean:
Iterative decoding beyond belief propagation. ITA 2010: 515-524 - [c35]Dung Viet Nguyen, Bane Vasic, Michael W. Marcellin, Shashi Kiran Chilappagari:
Structured LDPC codes from permutation matrices free of small trapping sets. ITW 2010: 1-5 - [i16]Shiva Kumar Planjery, David Declercq, Shashi Kiran Chilappagari, Bane Vasic:
Multilevel Decoders Surpassing Belief Propagation on the Binary Symmetric Channel. CoRR abs/1001.3421 (2010) - [i15]Shashi Kiran Chilappagari, Michael Chertkov, Bane Vasic:
Worst Configurations (Instantons) for Compressed Sensing over Reals: a Channel Coding Approach. CoRR abs/1001.5113 (2010) - [i14]Dung Viet Nguyen, Bane Vasic, Michael W. Marcellin, Shashi Kiran Chilappagari:
Structured LDPC Codes from Permutation Matrices Free of Small Trapping Sets. CoRR abs/1004.1198 (2010) - [i13]Dung Viet Nguyen, Shashi Kiran Chilappagari, Michael W. Marcellin, Bane Vasic:
LDPC Codes from Latin Squares Free of Small Trapping Sets. CoRR abs/1008.4177 (2010) - 2009
- [j20]Shashi Kiran Chilappagari, Michael Chertkov, Mikhail G. Stepanov, Bane Vasic:
Instanton-based techniques for analysis and reduction of error floors of LDPC codes. IEEE J. Sel. Areas Commun. 27(6): 855-865 (2009) - [j19]Shashi Kiran Chilappagari, Bane Vasic:
Error-correction capability of column-weight-three LDPC codes. IEEE Trans. Inf. Theory 55(5): 2055-2061 (2009) - [c34]Bane Vasic, Shashi Kiran Chilappagari, Dung Viet Nguyen, Shiva Kumar Planjery:
Trapping set ontology. Allerton 2009: 1-7 - [c31]Shashi Kiran Chilappagari, Bane Vasic, Mikhail G. Stepanov, Michael Chertkov:
Analysis of error floors of LDPC codes under LP decoding over the BSC. ISIT 2009: 379-383 - [c30]Shashi Kiran Chilappagari, David Declercq, Lucile Sassatelli, Bane Vasic:
Two-bit message passing decoders for LDPC codes over the binary symmetric channel. ISIT 2009: 2156-2160 - [i12]Lucile Sassatelli, Shashi Kiran Chilappagari, Bane Vasic, David Declercq:
Two-Bit Message Passing Decoders for LDPC Codes Over the Binary Symmetric Channel. CoRR abs/0901.2090 (2009) - [i11]Shashi Kiran Chilappagari, Michael Chertkov, Mikhail G. Stepanov, Bane Vasic:
Instanton-based Techniques for Analysis and Reduction of Error Floors of LDPC Codes. CoRR abs/0903.1624 (2009) - 2008
- [j18]Milos Ivkovic, Shashi Kiran Chilappagari, Bane Vasic:
Eliminating Trapping Sets in Low-Density Parity-Check Codes by Using Tanner Graph Covers. IEEE Trans. Inf. Theory 54(8): 3763-3768 (2008) - [c29]Shashi Kiran Chilappagari, Dung Viet Nguyen, Bane Vasic, Michael W. Marcellin:
Girth of the Tanner graph and error correction capability of LDPC codes. Allerton 2008: 1238-1245 - [c28]Shashi Kiran Chilappagari, Dung Viet Nguyen, Bane Vasic, Michael W. Marcellin:
On the guaranteed error correction capability of LDPC codes. ISIT 2008: 434-438 - [c27]Shashi Kiran Chilappagari, Anantha Raman Krishnan, Bane Vasic:
LDPC codes which can correct three errors under iterative decoding. ITW 2008: 406-410 - [i9]Shashi Kiran Chilappagari, Dung Viet Nguyen, Bane Vasic, Michael W. Marcellin:
On the guaranteed error correction capability of LDPC codes. CoRR abs/0801.1276 (2008) - [i8]Shashi Kiran Chilappagari, Anantha Raman Krishnan, Bane Vasic:
LDPC Codes Which Can Correct Three Errors Under Iterative Decoding. CoRR abs/0801.1282 (2008) - [i7]Milos Ivkovic, Shashi Kiran Chilappagari, Bane Vasic:
Eliminating Trapping Sets in Low-Density Parity Check Codes by using Tanner Graph Covers. CoRR abs/0805.1662 (2008) - [i6]Shashi Kiran Chilappagari, Dung Viet Nguyen, Bane Vasic, Michael W. Marcellin:
On Trapping Sets and Guaranteed Error Correction Capability of LDPC Codes and GLDPC Codes. CoRR abs/0805.2427 (2008) - [i5]Shashi Kiran Chilappagari, Dung Viet Nguyen, Bane Vasic, Michael W. Marcellin:
Error Correction Capability of Column-Weight-Three LDPC Codes: Part II. CoRR abs/0807.3582 (2008) - [i4]Shashi Kiran Chilappagari, Anantha Raman Krishnan, Bane Vasic, Michael W. Marcellin:
Low-Density Parity-Check Codes Which Can Correct Three Errors Under Iterative Decoding. CoRR abs/0810.1105 (2008) - 2007
- [j16]Bane Vasic, Shashi Kiran Chilappagari:
An Information Theoretical Framework for Analysis and Design of Nanoscale Fault-Tolerant Memories Based on Low-Density Parity-Check Codes. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(11): 2438-2446 (2007) - [c23]Milos Ivkovic, Shashi Kiran Chilappagari, Bane Vasic:
Designing LDPC Codes without small trapping sets by using Tanner Graph Covers. ISIT 2007: 2266-2270 - [i3]Shashi Kiran Chilappagari, Bane Vasic:
Reliable Memories Built from Unreliable Components Based on Expander Graphs. CoRR abs/0705.0044 (2007) - [i2]Shashi Kiran Chilappagari, Bane Vasic:
Error Correction Capability of Column-Weight-Three LDPC Codes. CoRR abs/0710.3427 (2007) - 2006
- [c20]Milos Ivkovic, Shashi Kiran Chilappagari, Bane Vasic:
Construction of Memory Circuits Using Unreliable Components Based on Low-Density Parity-Check Codes. GLOBECOM 2006 - [c18]Shashi Kiran Chilappagari, Sundararajan Sankaranarayanan, Bane Vasic:
Error Floors of LDPC Codes on the Binary Symmetric Channel. ICC 2006: 1089-1094 - [c15]Shashi Kiran Chilappagari, Milos Ivkovic, Bane Vasic:
Analysis of One Step Majority Logic Decoders Constructed From Faulty Gates. ISIT 2006: 469-473
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