Sudhakar Yalamanchili

◀ ▶ joint publications with Mitchelle Rasquinha

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Publications

2014
[c92]
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  - conf/ispass/WangBBCDKRRSXXY14
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Jun Wang, Jesse G. Beu, Rishiraj A. Bheda, Tom Conte, Zhenjiang Dong, Chad D. Kersey, Mitchelle Rasquinha, George F. Riley, William J. Song, He Xiao, Peng Xu, Sudhakar Yalamanchili:
Manifold: A parallel simulation framework for multicore systems. ISPASS 2014: 106-115
2011
[j26]
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  - journals/tvlsi/ChatterjeeRYM11
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  - https://dblp.org/rec/journals/tvlsi/ChatterjeeRYM11
Subho Chatterjee, Mitchelle Rasquinha, Sudhakar Yalamanchili, Saibal Mukhopadhyay:
A Scalable Design Methodology for Energy Minimization of STTRAM: A Circuit and Architecture Perspective. IEEE Trans. Very Large Scale Integr. Syst. 19(5): 809-817 (2011)
[c65]
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  - conf/IEEEpact/HassanCRY11
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Syed Minhaj Hassan, Dhruv Choudhary, Mitchelle Rasquinha, Sudhakar Yalamanchili:
Regulating Locality vs. Parallelism Tradeoffs in Multiple Memory Controller Environments. PACT 2011: 187-188
2010
[c56]
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  - conf/islped/RasquinhaCCMY10
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Mitchelle Rasquinha, Dhruv Choudhary, Subho Chatterjee, Saibal Mukhopadhyay, Sudhakar Yalamanchili:
An energy efficient cache design using spin torque transfer (STT) RAM. ISLPED 2010: 389-394
2009
[c55]
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  - conf/iccad/ChatterjeeRYM09
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Subho Chatterjee, Mitchelle Rasquinha, Sudhakar Yalamanchili, Saibal Mukhopadhyay:
A methodology for robust, energy efficient design of Spin-Torque-Transfer RAM arrays at scaled technologies. ICCAD 2009: 474-477

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