Peng Lu

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Chengyu Hu

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Publications

2020
[c61]
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  - conf/fpga/HuDLLWL20
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  - https://dblp.org/rec/conf/fpga/HuDLLWL20
Chengyu Hu, Qinghua Duan, Peng Lu, Wei Liu, Jian Wang, Jinmei Lai:
INTB: A New FPGA Interconnect Model for Architecture Exploration. FPGA 2020: 325
[c60]
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Chengyu Hu, Qinghua Duan, Peng Lu, Wei Liu, Jian Wang, Jinmei Lai:
A Tile-based Interconnect Model for FPGA Architecture Exploration. ACM Great Lakes Symposium on VLSI 2020: 113-118
2019
[c55]
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  - conf/asicon/LiuCHLL19
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Wei Liu, Weilin Cong, Chengyu Hu, Peng Lu, Jinmei Lai:
Balance of memory footprint and runtime for high-density routing in large-scale FPGAs. ASICON 2019: 1-4
[c54]
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  - conf/glvlsi/HuDHLLYWL19
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Chengyu Hu, Qinghua Duan, Liran Hu, Peng Lu, Zhengjie Li, Meng Yang, Jian Wang, Jinmei Lai:
An Analytical-based Hybrid Algorithm for FPGA Placement. ACM Great Lakes Symposium on VLSI 2019: 351-354
2018
[j27]
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  - journals/ieiceee/HuLYWL18
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Chengyu Hu, Peng Lu, Meng Yang, Jian Wang, Jinmei Lai:
A SA-based parallel method for FPGA placement. IEICE Electron. Express 15(24): 20180943 (2018)

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