Yusuke Niki

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Shinichi Sasaki

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Publications

2014
[j2]
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  - journals/jssc/TachibanaHTSKKSNSYU14
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  - https://dblp.org/rec/journals/jssc/TachibanaHTSKKSNSYU14
Fumihiko Tachibana, Osamu Hirabayashi, Yasuhisa Takeyama, Miyako Shizuno, Atsushi Kawasumi, Keiichi Kushida, Azuma Suzuki, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe, Yasuo Unekawa:
A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit. IEEE J. Solid State Circuits 49(1): 118-126 (2014)
2013
[c5]
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  dblp key:
  - conf/isscc/TachibanaHTSKKSNSYU13
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  - https://dblp.org/rec/conf/isscc/TachibanaHTSKKSNSYU13
Fumihiko Tachibana, Osamu Hirabayashi, Yasuhisa Takeyama, Miyako Shizuno, Atsushi Kawasumi, Keiichi Kushida, Azuma Suzuki, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe, Yasuo Unekawa:
A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit. ISSCC 2013: 320-321
2012
[c4]
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  dblp key:
  - conf/icicdt/KawasumiTHKTNSY12
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  - https://dblp.org/rec/conf/icicdt/KawasumiTHKTNSY12
Atsushi Kawasumi, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe:
Energy efficiency deterioration by variability in SRAM and circuit techniques for energy saving without voltage reduction. ICICDT 2012: 1-4
[c3]
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  - conf/vlsic/KawasumiTHKTNSY12
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  - https://dblp.org/rec/conf/vlsic/KawasumiTHKTNSY12
Atsushi Kawasumi, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe:
A 47% access time reduction with a worst-case timing-generation scheme utilizing a statistical method for ultra low voltage SRAMs. VLSIC 2012: 100-101
2011
[c2]
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  dblp key:
  - conf/asscc/KushidaHTHKSTFN11
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Keiichi Kushida, Osamu Hirabayashi, Fumihiko Tachibana, Hiroyuki Hara, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Yuki Fujimura, Yusuke Niki, Miyako Shizuno, Shinichi Sasaki, Tomoaki Yabe:
A trimless, 0.5V-1.0V wide voltage operation, high density SRAM macro utilizing dynamic cell stability monitor and multiple memory cell access. A-SSCC 2011: 161-164

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