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ORCIDMatthew K. Farrens
- > Home > Persons > Matthew K. Farrens
Publications
- 2001
[j7]Hsien-Hsin S. Lee, Gary S. Tyson, Matthew K. Farrens:
Improving Bandwidth Utilization using Eager Writeback. J. Instr. Level Parallelism 3 (2001)- 2000
- [c20]Hsien-Hsin S. Lee
, Gary S. Tyson, Matthew K. Farrens:
Eager writeback - a technique for improving bandwidth utilization. MICRO 2000: 11-21 - 1998
- [c18]Jude A. Rivers, Edward S. Tam, Gary S. Tyson, Edward S. Davidson, Matthew K. Farrens:
Utilizing Reuse Information in Data Cache Management. International Conference on Supercomputing 1998: 449-456 - 1997
- [j6]Gary S. Tyson, Matthew K. Farrens, John Matthews, Andrew R. Pleszkun:
Managing data caches using selective cache line replacement. Int. J. Parallel Program. 25(3): 213-242 (1997) - 1996
- [j3]Gary S. Tyson, Matthew K. Farrens:
Evaluating the Effects of Predicated Execution on Branch Prediction. Int. J. Parallel Program. 24(2): 159-186 (1996) - 1995
- [c16]Gary S. Tyson, Matthew K. Farrens, John Matthews, Andrew R. Pleszkun:
A modified approach to data cache management. MICRO 1995: 93-103 - 1994
- [j2]Gary S. Tyson, Matthew K. Farrens:
Code scheduling for multiple instruction stream architectures. Int. J. Parallel Program. 22(3): 243-272 (1994) - [c15]Matthew K. Farrens, Gary S. Tyson, Andrew R. Pleszkun:
A Study of Single-Chip Processor/Cache Organizations for Large Numbers of Transistors. ISCA 1994: 338-347 - 1993
- [c14]Matthew K. Farrens, Pius Ng, Phil Nico:
A comparision of superscalar and decoupled access/execute architectures. MICRO 1993: 100-103 - [c13]Gary S. Tyson, Matthew K. Farrens:
Techniques for extracting instruction level parallelism on MIMD architectures. MICRO 1993: 128-137 - 1992
- [c12]Matthew K. Farrens, Arvin Park, Allison Woodruff:
CCHIME: A Cache Coherent Hybrid Interconnected Memory Extension. IPPS 1992: 573-577 - [c11]Matthew K. Farrens, Arvin Park, Rob Fanfelle, Pius Ng, Gary S. Tyson:
A partitioned translation lookaside buffer approach to reducing address bandwith. ISCA 1992: 435 - [c10]Gary S. Tyson, Matthew K. Farrens, Andrew R. Pleszkun:
MISC: a Multiple Instruction Stream Computer. MICRO 1992: 193-196 - [c9]Matthew K. Farrens, Arvin Park, Gary S. Tyson:
Modifying VM hardware to reduce address pin requirements. MICRO 1992: 210-213 - 1991
- [j1]Matthew K. Farrens, Andrew R. Pleszkun:
Implementation of the PIPE Processor. Computer 24(1): 65-69 (1991) - [c8]Matthew K. Farrens, Arvin Park:
Dynamic Base Register Caching: A Technique for Reducing Address Bus Width. ISCA 1991: 128-137 - [c7]Matthew K. Farrens, Andrew R. Pleszkun:
Strategies for Achieving Improved Processor Throughput. ISCA 1991: 362-369 - [c6]Jeffrey C. Becker, Arvin Park, Matthew K. Farrens:
An Analysis of the Information Content of Address Reference Streams. MICRO 1991: 19-24 - [c5]Matthew K. Farrens, Arvin Park:
Workload and Implementation Considerations for Dynamic Base Register Caching. MICRO 1991: 62-68 - [c4]Matthew K. Farrens, Brad Wetmore, Allison Woodruff:
Alleviation of tree saturation in multistage interconnection networks. SC 1991: 400-409 - 1990
- [c3]Arvin Park, Matthew K. Farrens:
Address compression through base register caching. MICRO 1990: 193-199 - [c2]Matthew K. Farrens, Andrew R. Pleszkun:
An evaluation of functional unit lengths for single-chip processors. MICRO 1990: 209-215 - 1989
- [c1]Matthew K. Farrens, Andrew R. Pleszkun:
Improving Performance of Small On-Chip Instruction Caches. ISCA 1989: 234-241
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