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ORCIDVinicius N. Possani
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- affiliation (PhD 2019): Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil
- affiliation: Federal University of Pelotas, Development Technology Center, Brazil
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Journal Articles
- 2020
[j4]Walter Lau Neto
, Vinicius N. Possani, Felipe S. Marranghello, Jody Maick Matos, Pierre-Emmanuel Gaillardon, André Inácio Reis, Renato Perez Ribas:
Exact Benchmark Circuits for Logic Synthesis. IEEE Des. Test 37(3): 51-58 (2020)- [j3]Vinicius N. Possani, Alan Mishchenko, Renato P. Ribas, André Inácio Reis:
Parallel Combinational Equivalence Checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 3081-3092 (2020) - 2017
- [j2]Vinicius N. Possani, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar S. da Rosa Jr.:
Transistor Count Optimization in IG FinFET Network Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(9): 1483-1496 (2017) - 2016
- [j1]Vinicius Neves Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Leomar Soares da Rosa Jr.:
Graph-Based Transistor Network Generation Method for Supergate Design. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 692-705 (2016)
Conference and Workshop Papers
- 2022
- [c12]Giulia Meuli, Vinicius N. Possani, Rajinder Singh, Siang-Yun Lee, Alessandro Tempia Calvino, Dewmini Sudara Marakkalage, Patrick Vuillod, Luca G. Amarù, Scott Chase, Jamil Kawa, Giovanni De Micheli:
Majority-based Design Flow for AQFP Superconducting Family. DATE 2022: 34-39 - 2021
- [c11]Luca Gaetano Amarù, Vinicius N. Possani, Eleonora Testa, Felipe S. Marranghello, Christopher Casares, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli:
LUT-Based Optimization For ASIC Design Flow. DAC 2021: 871-876 - 2020
- [c10]Luca G. Amarù, Felipe S. Marranghello, Eleonora Testa, Christopher Casares, Vinicius N. Possani, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli:
SAT-Sweeping Enhanced for Logic Synthesis. DAC 2020: 1-6 - 2018
- [c9]Vinicius N. Possani, Yi-Shan Lu, Alan Mishchenko, Keshav Pingali, Renato P. Ribas, André Inácio Reis:
Unlocking fine-grain parallelism for AIG rewriting. ICCAD 2018: 87 - [c8]Walter Lau Neto, Vinicius N. Possani, Felipe S. Marranghello, Jody Maick Matos, André Inácio Reis, Renato P. Ribas:
Exact Multi-Level Benchmark Circuit Generation for Logic Synthesis Evaluation. SBCCI 2018: 1-6 - 2017
- [c7]Jeferson José Baqueta, Felipe S. Marranghello, Vinicius N. Possani, Augusto Neutzling, André Inácio Reis, Renato P. Ribas:
Binary adder circuit design using emerging MIGFET devices. ISQED 2017: 125-130 - 2016
- [c6]Andres M. A. Valdes, Vinicius N. Possani, Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas:
Performance evaluation of optimized transistor networks built using independent-gate FinFET. LASCAS 2016: 227-230 - 2014
- [c5]Vinicius N. Possani, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar Soares da Rosa Jr.:
Exploring Independent Gates in FinFET-Based Transistor Network Generation. SBCCI 2014: 41:1-41:6 - 2013
- [c4]Vinicius N. Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Leomar Soares da Rosa Jr.:
Efficient transistor-level design of CMOS gates. ACM Great Lakes Symposium on VLSI 2013: 191-196 - [c3]Vinicius N. Possani, Felipe S. Marques, Leomar S. da Rosa Jr., Vinicius Callegaro, André Inácio Reis, Renato P. Ribas:
Transistor-level optimization of CMOS complex gates. LASCAS 2013: 1-4 - [c2]Vinicius N. Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar S. da Rosa Jr.:
Improving the methodology to build non-series-parallel transistor arrangements. SBCCI 2013: 1-6 - 2012
- [c1]Vinicius N. Possani, Felipe S. Marques, Leomar S. da Rosa Jr., Vinicius Callegaro, André Inácio Reis, Renato P. Ribas:
NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements. SBCCI 2012: 1-6
Coauthor Index
aka: Renato Perez Ribas
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