BibTeX records: Syed Suhaib

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@inproceedings{DBLP:conf/vts/LiuKHSR24,
  author       = {Mingjie Liu and
                  Minwoo Kang and
                  Ghaith Bany Hamad and
                  Syed Suhaib and
                  Haoxing Ren},
  title        = {Domain-Adapted LLMs for {VLSI} Design and Verification: {A} Case Study
                  on Formal Verification},
  booktitle    = {42nd {IEEE} {VLSI} Test Symposium, {VTS} 2024, Tempe, AZ, USA, April
                  22-24, 2024},
  pages        = {1--4},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/VTS60656.2024.10538589},
  doi          = {10.1109/VTS60656.2024.10538589},
  timestamp    = {Mon, 03 Jun 2024 16:53:11 +0200},
  biburl       = {https://dblp.org/rec/conf/vts/LiuKHSR24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/SuhaibMS08,
  author       = {Syed Suhaib and
                  Deepak Mathaikutty and
                  Sandeep K. Shukla},
  title        = {A Trace-Based Framework for Verifiable {GALS} Composition of IPs},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {16},
  number       = {9},
  pages        = {1176--1186},
  year         = {2008},
  url          = {https://doi.org/10.1109/TVLSI.2008.2000869},
  doi          = {10.1109/TVLSI.2008.2000869},
  timestamp    = {Wed, 11 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/SuhaibMS08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/fdl/SuhaibJSM08,
  author       = {Syed Suhaib and
                  Bijoy Antony Jose and
                  Sandeep K. Shukla and
                  Deepak Mathaikutty},
  title        = {Formal Transformation of a {KPN} Specification to a {GALS} Implementation},
  booktitle    = {Forum on specification and Design Languages, {FDL} 2008, September
                  23-25, 2008, Stuttgart, Germany, Proceedings},
  pages        = {84--89},
  publisher    = {{IEEE}},
  year         = {2008},
  url          = {https://doi.org/10.1109/FDL.2008.4641426},
  doi          = {10.1109/FDL.2008.4641426},
  timestamp    = {Wed, 16 Oct 2019 14:14:54 +0200},
  biburl       = {https://dblp.org/rec/conf/fdl/SuhaibJSM08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@phdthesis{DBLP:phd/basesearch/Suhaib07,
  author       = {Syed Suhaib},
  title        = {Formal Methods for Intellectual Property Composition Across Synchronization
                  Domains},
  school       = {Virginia Tech, Blacksburg, VA, {USA}},
  year         = {2007},
  url          = {https://hdl.handle.net/10919/28952},
  timestamp    = {Wed, 04 May 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/phd/basesearch/Suhaib07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:journals/entcs/SuhaibMS08,
  author       = {Syed Suhaib and
                  Deepak Mathaikutty and
                  Sandeep K. Shukla},
  editor       = {Alain Girault and
                  Robert de Simone},
  title        = {Dataflow Architectures for {GALS}},
  booktitle    = {Proceedings of the Third International Workshop on Formal Methods
                  for Globally Asynchronous Locally Synchronous Design, FMGALS@MEMOCODE
                  2007, Nice, France, May 29, 2007},
  series       = {Electronic Notes in Theoretical Computer Science},
  volume       = {200},
  number       = {1},
  pages        = {33--50},
  publisher    = {Elsevier},
  year         = {2007},
  url          = {https://doi.org/10.1016/j.entcs.2008.02.005},
  doi          = {10.1016/J.ENTCS.2008.02.005},
  timestamp    = {Mon, 13 Feb 2023 09:40:48 +0100},
  biburl       = {https://dblp.org/rec/journals/entcs/SuhaibMS08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tc/SuhaibMBS06,
  author       = {Syed Suhaib and
                  Deepak Mathaikutty and
                  David Berner and
                  Sandeep K. Shukla},
  title        = {Validating Families of Latency Insensitive Protocols},
  journal      = {{IEEE} Trans. Computers},
  volume       = {55},
  number       = {11},
  pages        = {1391--1401},
  year         = {2006},
  url          = {https://doi.org/10.1109/TC.2006.188},
  doi          = {10.1109/TC.2006.188},
  timestamp    = {Sat, 20 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tc/SuhaibMBS06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/hldvt/SuhaibMST06,
  author       = {Syed Suhaib and
                  Deepak Mathaikutty and
                  Sandeep K. Shukla and
                  Jean{-}Pierre Talpin},
  title        = {Polychronous Methodology For System Design: {A} True Concurrency Approach},
  booktitle    = {Eleventh Annual {IEEE} International High-Level Design Validation
                  and Test Workshop 2006, Monterey, CA, USA, Nov 9-10, 2006},
  pages        = {211--214},
  publisher    = {{IEEE} Computer Society},
  year         = {2006},
  url          = {https://doi.org/10.1109/HLDVT.2006.319993},
  doi          = {10.1109/HLDVT.2006.319993},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/hldvt/SuhaibMST06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/socc/SuhaibMS06,
  author       = {Syed Suhaib and
                  Deepak Mathaikutty and
                  Sandeep K. Shukla},
  title        = {A Trace Based Framework for Validation of SoC Designs with {GALS}
                  Systems},
  booktitle    = {2006 {IEEE} International {SOC} Conference, Austin, Texas, USA, September
                  24-27, 2006},
  pages        = {247--250},
  publisher    = {{IEEE}},
  year         = {2006},
  url          = {https://doi.org/10.1109/SOCC.2006.283891},
  doi          = {10.1109/SOCC.2006.283891},
  timestamp    = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl       = {https://dblp.org/rec/conf/socc/SuhaibMS06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/SuhaibMSB05,
  author       = {Syed Suhaib and
                  Deepak Mathaikutty and
                  Sandeep K. Shukla and
                  David Berner},
  title        = {{XFM:} An incremental methodology for developing formal models},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {10},
  number       = {4},
  pages        = {589--609},
  year         = {2005},
  url          = {https://doi.org/10.1145/1109118.1109120},
  doi          = {10.1145/1109118.1109120},
  timestamp    = {Wed, 14 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/SuhaibMSB05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/hldvt/SuhaibMSB05,
  author       = {Syed Suhaib and
                  Deepak Mathaikutty and
                  Sandeep K. Shukla and
                  David Berner},
  title        = {Validating families of latency insensitive protocols},
  booktitle    = {Tenth {IEEE} International High-Level Design Validation and Test Workshop
                  2005, Napa Valley, CA, USA, November 30 - December 2, 2005},
  pages        = {127--134},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/HLDVT.2005.1568826},
  doi          = {10.1109/HLDVT.2005.1568826},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/hldvt/SuhaibMSB05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/socc/SuhaibMS05,
  author       = {Syed Suhaib and
                  Deepak Mathaikutty and
                  Sandeep K. Shukla},
  title        = {System Level Design Methodology for System On Chips using Multi-Threaded
                  Graphs},
  booktitle    = {Proceedings 2005 {IEEE} International {SOC} Conference, September
                  25-28, 2005, Washington Dulles Airport, Herndon, VA, {USA}},
  pages        = {133--136},
  publisher    = {{IEEE}},
  year         = {2005},
  url          = {https://doi.org/10.1109/SOCC.2005.1554480},
  doi          = {10.1109/SOCC.2005.1554480},
  timestamp    = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl       = {https://dblp.org/rec/conf/socc/SuhaibMS05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:journals/entcs/SuhaibMSBT06,
  author       = {Syed Suhaib and
                  Deepak Mathaikutty and
                  Sandeep K. Shukla and
                  David Berner and
                  Jean{-}Pierre Talpin},
  editor       = {Montek Singh and
                  Jean{-}Pierre Talpin},
  title        = {A Functional Programming Framework for Latency Insensitive Protocol
                  Validation},
  booktitle    = {Proceedings of the Second Workshop on Globally Asynchronous, Locally
                  Synchronous Design, FMGALS@MEMOCODE 2005, Verona, Italy, July 15,
                  2005},
  series       = {Electronic Notes in Theoretical Computer Science},
  volume       = {146},
  number       = {2},
  pages        = {169--188},
  publisher    = {Elsevier},
  year         = {2005},
  url          = {https://doi.org/10.1016/j.entcs.2005.05.041},
  doi          = {10.1016/J.ENTCS.2005.05.041},
  timestamp    = {Fri, 16 Dec 2022 11:32:05 +0100},
  biburl       = {https://dblp.org/rec/journals/entcs/SuhaibMSBT06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tse/LiRSF04,
  author       = {Peng Li and
                  Binoy Ravindran and
                  Syed Suhaib and
                  Shahrooz Feizabadi},
  title        = {A Formally Verified Application-Level Framework for Real-Time Scheduling
                  on {POSIX} Real-Time Operating Systems},
  journal      = {{IEEE} Trans. Software Eng.},
  volume       = {30},
  number       = {9},
  pages        = {613--629},
  year         = {2004},
  url          = {https://doi.org/10.1109/TSE.2004.45},
  doi          = {10.1109/TSE.2004.45},
  timestamp    = {Sun, 01 Jul 2018 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tse/LiRSF04.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/hldvt/SuhaibMS04,
  author       = {Syed Suhaib and
                  Deepak Mathaikutty and
                  Sandeep K. Shukla},
  title        = {Effects of property ordering in an incremental formal modeling methodology},
  booktitle    = {Ninth {IEEE} International High-Level Design Validation and Test Workshop
                  2004, Sonoma Valley, CA, USA, November 10-12, 2004},
  pages        = {89--94},
  publisher    = {{IEEE} Computer Society},
  year         = {2004},
  url          = {https://doi.org/10.1109/HLDVT.2004.1431245},
  doi          = {10.1109/HLDVT.2004.1431245},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/hldvt/SuhaibMS04.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/mtv/SuhaibMSB04,
  author       = {Syed Suhaib and
                  Deepak Mathaikutty and
                  Sandeep K. Shukla and
                  David Berner},
  title        = {Extreme Formal Modeling {(XFM)} for Hardware Models},
  booktitle    = {Fifth International Workshop on Microprocessor Test and Verification
                  {(MTV} 2004), Common Challenges and Solutions, 08-10 September 2004,
                  Austin, Texas, {USA}},
  pages        = {30--35},
  publisher    = {{IEEE} Computer Society},
  year         = {2004},
  url          = {https://doi.org/10.1109/MTV.2004.8},
  doi          = {10.1109/MTV.2004.8},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/mtv/SuhaibMSB04.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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