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ORCIDBibTeX records: Irith Pomeranz
@article{DBLP:journals/access/Pomeranz24,
author = {Irith Pomeranz},
title = {Longest Path Selection Based on Path Identifiers},
journal = {{IEEE} Access},
volume = {12},
pages = {14512--14520},
year = {2024},
url = {https://doi.org/10.1109/ACCESS.2024.3357754},
doi = {10.1109/ACCESS.2024.3357754},
timestamp = {Thu, 29 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/access/Pomeranz24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/Pomeranz24a,
author = {Irith Pomeranz},
title = {Sharing of Topped-Off Compressed Test Sets Among Logic Blocks},
journal = {{IEEE} Access},
volume = {12},
pages = {49895--49903},
year = {2024},
url = {https://doi.org/10.1109/ACCESS.2024.3385442},
doi = {10.1109/ACCESS.2024.3385442},
timestamp = {Sat, 04 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/access/Pomeranz24a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/Pomeranz24,
author = {Irith Pomeranz},
title = {Conventional Tests for Approximate Scan Logic},
journal = {{IEEE} Des. Test},
volume = {41},
number = {3},
pages = {5--13},
year = {2024},
url = {https://doi.org/10.1109/MDAT.2024.3370824},
doi = {10.1109/MDAT.2024.3370824},
timestamp = {Mon, 06 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/Pomeranz24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz24,
author = {Irith Pomeranz},
title = {Dynamic Test Compaction of a Compressed Test Set Shared Among Logic
Blocks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {43},
number = {1},
pages = {394--402},
year = {2024},
url = {https://doi.org/10.1109/TCAD.2023.3307352},
doi = {10.1109/TCAD.2023.3307352},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JoeMPR24,
author = {Jerin Joe and
Nilanjan Mukherjee and
Irith Pomeranz and
Janusz Rajski},
title = {Generation of Two-Cycle Tests for Structurally Similar Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {43},
number = {2},
pages = {694--703},
year = {2024},
url = {https://doi.org/10.1109/TCAD.2023.3321973},
doi = {10.1109/TCAD.2023.3321973},
timestamp = {Thu, 29 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/JoeMPR24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz24a,
author = {Irith Pomeranz},
title = {Test Insertion for Dynamic Test Compaction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {43},
number = {4},
pages = {1302--1306},
year = {2024},
url = {https://doi.org/10.1109/TCAD.2023.3332835},
doi = {10.1109/TCAD.2023.3332835},
timestamp = {Mon, 01 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz24a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz24,
author = {Irith Pomeranz},
title = {Testability Evaluation for Local Design Modifications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {1},
pages = {195--199},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3321572},
doi = {10.1109/TVLSI.2023.3321572},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz24a,
author = {Irith Pomeranz},
title = {Bit-Complemented Test Data to Replace the Tail of a Fault Coverage
Curve},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {4},
pages = {609--618},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3365355},
doi = {10.1109/TVLSI.2024.3365355},
timestamp = {Mon, 01 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz24a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/Pomeranz23,
author = {Irith Pomeranz},
title = {Storage and Counter Based Logic Built-In Self-Test},
journal = {{IEEE} Access},
volume = {11},
pages = {139335--139344},
year = {2023},
url = {https://doi.org/10.1109/ACCESS.2023.3341360},
doi = {10.1109/ACCESS.2023.3341360},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/access/Pomeranz23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz23,
author = {Irith Pomeranz},
title = {Topping Off Test Sets Under Bounded Transparent Scan},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {42},
number = {1},
pages = {341--345},
year = {2023},
url = {https://doi.org/10.1109/TCAD.2022.3167885},
doi = {10.1109/TCAD.2022.3167885},
timestamp = {Sun, 15 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz23a,
author = {Irith Pomeranz},
title = {Functionally Possible Scan-Based Test Set as a Dual of a Compressed
Multicycle Test Set},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {42},
number = {4},
pages = {1336--1345},
year = {2023},
url = {https://doi.org/10.1109/TCAD.2022.3193902},
doi = {10.1109/TCAD.2022.3193902},
timestamp = {Sun, 16 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz23a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz23b,
author = {Irith Pomeranz},
title = {Estimating the Number of Extra Tests During Iterative Test Generation
for Single-Cycle Gate-Exhaustive Faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {42},
number = {8},
pages = {2752--2760},
year = {2023},
url = {https://doi.org/10.1109/TCAD.2022.3226677},
doi = {10.1109/TCAD.2022.3226677},
timestamp = {Sat, 05 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz23b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz23c,
author = {Irith Pomeranz},
title = {Storage-Based Logic Built-In Self-Test With Cyclic Tests},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {42},
number = {9},
pages = {3118--3122},
year = {2023},
url = {https://doi.org/10.1109/TCAD.2022.3233737},
doi = {10.1109/TCAD.2022.3233737},
timestamp = {Thu, 14 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz23c.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz23d,
author = {Irith Pomeranz},
title = {Partially Specified Output Response for Reduced Fail Data Volume},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {42},
number = {9},
pages = {3123--3127},
year = {2023},
url = {https://doi.org/10.1109/TCAD.2022.3233319},
doi = {10.1109/TCAD.2022.3233319},
timestamp = {Thu, 14 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz23d.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz23,
author = {Irith Pomeranz},
title = {Path Unselection for Path Delay Fault Test Generation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {2},
pages = {267--275},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3224361},
doi = {10.1109/TVLSI.2022.3224361},
timestamp = {Fri, 10 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz23a,
author = {Irith Pomeranz},
title = {Diagnostic Test Point Insertion and Test Compaction},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {2},
pages = {276--285},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3218924},
doi = {10.1109/TVLSI.2022.3218924},
timestamp = {Fri, 10 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz23a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz23b,
author = {Irith Pomeranz},
title = {Sharing of Compressed Tests Among Logic Blocks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {4},
pages = {421--430},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3244804},
doi = {10.1109/TVLSI.2023.3244804},
timestamp = {Sun, 16 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz23b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz23c,
author = {Irith Pomeranz},
title = {Test Data Compression for Transparent-Scan Sequences},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {4},
pages = {601--605},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3240505},
doi = {10.1109/TVLSI.2023.3240505},
timestamp = {Sun, 16 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz23c.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz23d,
author = {Irith Pomeranz},
title = {Storage-Based Logic Built-In Self-Test With Partitioned Deterministic
Compressed Tests},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {9},
pages = {1259--1268},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3285691},
doi = {10.1109/TVLSI.2023.3285691},
timestamp = {Thu, 14 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz23d.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz23e,
author = {Irith Pomeranz},
title = {Dummy Faulty Units for Reduced Fail Data Volume From Logic Faults},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {11},
pages = {1754--1762},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3304380},
doi = {10.1109/TVLSI.2023.3304380},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz23e.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/Pomeranz23,
author = {Irith Pomeranz},
title = {Compaction of Functional Broadside Tests for Path Delay Faults Using
Clusters of Propagation Lines},
booktitle = {{IEEE} International Test Conference, {ITC} 2023, Anaheim, CA, USA,
October 7-15, 2023},
pages = {105--110},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ITC51656.2023.00025},
doi = {10.1109/ITC51656.2023.00025},
timestamp = {Tue, 09 Jan 2024 17:03:11 +0100},
biburl = {https://dblp.org/rec/conf/itc/Pomeranz23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/GopalsamyP23,
author = {Subashini Gopalsamy and
Irith Pomeranz},
title = {Fully Deterministic Storage Based Logic Built-In Self-Test},
booktitle = {41st {IEEE} {VLSI} Test Symposium, {VTS} 2023, San Diego, CA, USA,
April 24-26, 2023},
pages = {1--7},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VTS56346.2023.10139967},
doi = {10.1109/VTS56346.2023.10139967},
timestamp = {Fri, 09 Jun 2023 15:18:15 +0200},
biburl = {https://dblp.org/rec/conf/vts/GopalsamyP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/Pomeranz23,
author = {Irith Pomeranz},
title = {Expanding a Pool of Functional Test Sequences to Support Test Compaction},
booktitle = {41st {IEEE} {VLSI} Test Symposium, {VTS} 2023, San Diego, CA, USA,
April 24-26, 2023},
pages = {1--7},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VTS56346.2023.10139927},
doi = {10.1109/VTS56346.2023.10139927},
timestamp = {Fri, 09 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vts/Pomeranz23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/Pomeranz23a,
author = {Irith Pomeranz},
title = {Compact Set of Functional Broadside Tests with Fault Detection on
Primary Outputs},
booktitle = {41st {IEEE} {VLSI} Test Symposium, {VTS} 2023, San Diego, CA, USA,
April 24-26, 2023},
pages = {1--7},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VTS56346.2023.10140078},
doi = {10.1109/VTS56346.2023.10140078},
timestamp = {Fri, 09 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vts/Pomeranz23a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz22,
author = {Irith Pomeranz},
title = {Efficient Identification of Undetectable Two-Cycle Gate-Exhaustive
Faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {41},
number = {3},
pages = {776--783},
year = {2022},
url = {https://doi.org/10.1109/TCAD.2021.3062767},
doi = {10.1109/TCAD.2021.3062767},
timestamp = {Tue, 15 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz22a,
author = {Irith Pomeranz},
title = {Static Test Compaction Using Independent Suffixes of a Transparent-Scan
Sequence},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {41},
number = {4},
pages = {1130--1141},
year = {2022},
url = {https://doi.org/10.1109/TCAD.2021.3073625},
doi = {10.1109/TCAD.2021.3073625},
timestamp = {Fri, 01 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz22a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz22b,
author = {Irith Pomeranz},
title = {Multicycle Tests With Fault Detection Test Data for Improved Logic
Diagnosis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {41},
number = {5},
pages = {1587--1591},
year = {2022},
url = {https://doi.org/10.1109/TCAD.2021.3079146},
doi = {10.1109/TCAD.2021.3079146},
timestamp = {Wed, 18 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz22b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz22c,
author = {Irith Pomeranz},
title = {GEPDFs: Path Delay Faults Based on Two-Cycle Gate-Exhaustive Faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {41},
number = {7},
pages = {2315--2322},
year = {2022},
url = {https://doi.org/10.1109/TCAD.2021.3105913},
doi = {10.1109/TCAD.2021.3105913},
timestamp = {Tue, 28 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz22c.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz22d,
author = {Irith Pomeranz},
title = {Storage-Based Logic Built-in Self-Test With Multicycle Tests},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {41},
number = {10},
pages = {3553--3557},
year = {2022},
url = {https://doi.org/10.1109/TCAD.2021.3128446},
doi = {10.1109/TCAD.2021.3128446},
timestamp = {Tue, 18 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz22d.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz22e,
author = {Irith Pomeranz},
title = {Pass/Fail Data for Logic Diagnosis Under Bounded Transparent Scan},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {41},
number = {11},
pages = {4862--4872},
year = {2022},
url = {https://doi.org/10.1109/TCAD.2021.3134901},
doi = {10.1109/TCAD.2021.3134901},
timestamp = {Sun, 13 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz22e.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz22f,
author = {Irith Pomeranz},
title = {Wrapping Paths of Undetected Transition Faults With Two-Cycle Gate-Exhaustive
Faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {41},
number = {12},
pages = {5635--5643},
year = {2022},
url = {https://doi.org/10.1109/TCAD.2022.3154711},
doi = {10.1109/TCAD.2022.3154711},
timestamp = {Mon, 05 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz22f.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/Pomeranz22,
author = {Irith Pomeranz},
title = {Increasing the Fault Coverage of a Truncated Test Set},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {27},
number = {6},
pages = {54:1--54:16},
year = {2022},
url = {https://doi.org/10.1145/3508459},
doi = {10.1145/3508459},
timestamp = {Sun, 15 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/Pomeranz22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz22,
author = {Irith Pomeranz},
title = {Preponing Fault Detections for Test Compaction Under Transparent Scan},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {10},
pages = {1543--1547},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3189804},
doi = {10.1109/TVLSI.2022.3189804},
timestamp = {Tue, 18 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz22a,
author = {Irith Pomeranz},
title = {Test Sequences for Faults in the Scan Logic},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {10},
pages = {1568--1572},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3182540},
doi = {10.1109/TVLSI.2022.3182540},
timestamp = {Tue, 18 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz22a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz22b,
author = {Irith Pomeranz},
title = {Functional Test Sequences as a Source for Partially Functional Launch-on-Shift
Tests},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {11},
pages = {1803--1807},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3198523},
doi = {10.1109/TVLSI.2022.3198523},
timestamp = {Sun, 13 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz22b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/Pomeranz22,
author = {Irith Pomeranz},
title = {Two-Dimensional Test Generation Objective},
booktitle = {{IEEE} 31st Asian Test Symposium, {ATS} 2022, Taichung City, Taiwan,
November 21-24, 2022},
pages = {108--113},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ATS56056.2022.00031},
doi = {10.1109/ATS56056.2022.00031},
timestamp = {Wed, 11 Jan 2023 14:55:55 +0100},
biburl = {https://dblp.org/rec/conf/ats/Pomeranz22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/Pomeranz22a,
author = {Irith Pomeranz},
title = {Selecting Path Delay Faults Through the Largest Subcircuits of Uncovered
Lines},
booktitle = {{IEEE} 31st Asian Test Symposium, {ATS} 2022, Taichung City, Taiwan,
November 21-24, 2022},
pages = {114--119},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ATS56056.2022.00032},
doi = {10.1109/ATS56056.2022.00032},
timestamp = {Wed, 11 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/Pomeranz22a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/AddepalliPANSV22,
author = {Hari Addepalli and
Irith Pomeranz and
M. Enamul Amyeen and
Suriyaprakash Natarajan and
Arani Sinha and
Srikanth Venkataraman},
title = {Using Fault Detection Tests to Produce Diagnostic Tests Targeting
Large Sets of Candidate Faults},
booktitle = {{IEEE} 31st Asian Test Symposium, {ATS} 2022, Taichung City, Taiwan,
November 21-24, 2022},
pages = {120--125},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ATS56056.2022.00033},
doi = {10.1109/ATS56056.2022.00033},
timestamp = {Wed, 11 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/AddepalliPANSV22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/Pomeranz22b,
author = {Irith Pomeranz},
title = {Usable Circuits with Imperfect Scan Logic},
booktitle = {{IEEE} 31st Asian Test Symposium, {ATS} 2022, Taichung City, Taiwan,
November 21-24, 2022},
pages = {156--161},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ATS56056.2022.00039},
doi = {10.1109/ATS56056.2022.00039},
timestamp = {Wed, 11 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/Pomeranz22b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/Pomeranz22,
author = {Irith Pomeranz},
editor = {Luca Cassano and
Sreejit Chakravarty and
Alberto Bosio},
title = {Storage-Based Logic Built-In Self-Test with Variable-Length Test Data},
booktitle = {{IEEE} International Symposium on Defect and Fault Tolerance in {VLSI}
and Nanotechnology Systems, {DFT} 2022, Austin, TX, USA, October 19-21,
2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/DFT56152.2022.9962357},
doi = {10.1109/DFT56152.2022.9962357},
timestamp = {Thu, 08 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dft/Pomeranz22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/Pomeranz22,
author = {Irith Pomeranz},
editor = {Ioannis Savidis and
Avesta Sasan and
Himanshu Thapliyal and
Ronald F. DeMara},
title = {Compaction of Compressed Bounded Transparent-Scan Test Sets},
booktitle = {{GLSVLSI} '22: Great Lakes Symposium on {VLSI} 2022, Irvine {CA} USA,
June 6 - 8, 2022},
pages = {339--343},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3526241.3530358},
doi = {10.1145/3526241.3530358},
timestamp = {Fri, 03 Jun 2022 08:45:20 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/Pomeranz22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/AddepalliP22,
author = {Hari Addepalli and
Irith Pomeranz},
editor = {Ioannis Savidis and
Avesta Sasan and
Himanshu Thapliyal and
Ronald F. DeMara},
title = {Algorithms for the Selection of Applied Tests when a Stored Test Produces
Many Applied Tests},
booktitle = {{GLSVLSI} '22: Great Lakes Symposium on {VLSI} 2022, Irvine {CA} USA,
June 6 - 8, 2022},
pages = {345--349},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3526241.3530359},
doi = {10.1145/3526241.3530359},
timestamp = {Fri, 03 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/AddepalliP22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/Joe0PR22,
author = {Jerin Joe and
Nilanjan Mukherjee and
Irith Pomeranz and
Janusz Rajski},
title = {Test Generation for an Iterative Design Flow with {RTL} Changes},
booktitle = {{IEEE} International Test Conference, {ITC} 2022, Anaheim, CA, USA,
September 23-30, 2022},
pages = {305--313},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ITC50671.2022.00039},
doi = {10.1109/ITC50671.2022.00039},
timestamp = {Thu, 05 Jan 2023 13:13:27 +0100},
biburl = {https://dblp.org/rec/conf/itc/Joe0PR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/Pomeranz22,
author = {Irith Pomeranz},
title = {Transforming an {\textdollar}n{\textdollar}-Detection Test Set into
a Test Set for a Variety of Fault Models},
booktitle = {{IEEE} International Test Conference, {ITC} 2022, Anaheim, CA, USA,
September 23-30, 2022},
pages = {474--478},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ITC50671.2022.00055},
doi = {10.1109/ITC50671.2022.00055},
timestamp = {Thu, 05 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/Pomeranz22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/JoeMPR22,
author = {Jerin Joe and
Nilanjan Mukherjee and
Irith Pomeranz and
Janusz Rajski},
title = {Fast Test Generation for Structurally Similar Circuits},
booktitle = {40th {IEEE} {VLSI} Test Symposium, {VTS} 2022, San Diego, CA, USA,
April 25-27, 2022},
pages = {1--7},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VTS52500.2021.9794232},
doi = {10.1109/VTS52500.2021.9794232},
timestamp = {Wed, 22 Jun 2022 15:24:48 +0200},
biburl = {https://dblp.org/rec/conf/vts/JoeMPR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz21,
author = {Irith Pomeranz},
title = {Maximal Independent Fault Set for Gate-Exhaustive Faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {40},
number = {3},
pages = {598--602},
year = {2021},
url = {https://doi.org/10.1109/TCAD.2020.3003289},
doi = {10.1109/TCAD.2020.3003289},
timestamp = {Tue, 02 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz21a,
author = {Irith Pomeranz},
title = {{PRESERVE:} Static Test Compaction that Preserves Individual Numbers
of Tests},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {40},
number = {4},
pages = {803--807},
year = {2021},
url = {https://doi.org/10.1109/TCAD.2020.3005371},
doi = {10.1109/TCAD.2020.3005371},
timestamp = {Thu, 29 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz21a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz21b,
author = {Irith Pomeranz},
title = {Padding of {LFSR} Seeds for Reduced Input Test Data Volume},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {40},
number = {5},
pages = {1004--1008},
year = {2021},
url = {https://doi.org/10.1109/TCAD.2020.3011665},
doi = {10.1109/TCAD.2020.3011665},
timestamp = {Thu, 29 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz21b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzA21,
author = {Irith Pomeranz and
M. Enamul Amyeen},
title = {Hybrid Pass/Fail and Full Fail Data for Reduced Fail Data Volume},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {40},
number = {8},
pages = {1711--1720},
year = {2021},
url = {https://doi.org/10.1109/TCAD.2020.3025091},
doi = {10.1109/TCAD.2020.3025091},
timestamp = {Thu, 29 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzA21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz21c,
author = {Irith Pomeranz},
title = {Storage-Based Built-In Self-Test for Gate-Exhaustive Faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {40},
number = {10},
pages = {2189--2193},
year = {2021},
url = {https://doi.org/10.1109/TCAD.2020.3035133},
doi = {10.1109/TCAD.2020.3035133},
timestamp = {Tue, 05 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz21c.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/PomeranzA21,
author = {Irith Pomeranz and
M. Enamul Amyeen},
title = {Logic Diagnosis with Hybrid Fail Data},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {26},
number = {3},
pages = {19:1--19:13},
year = {2021},
url = {https://doi.org/10.1145/3433929},
doi = {10.1145/3433929},
timestamp = {Tue, 16 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/PomeranzA21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/Pomeranz21,
author = {Irith Pomeranz},
title = {Covering Test Holes of Functional Broadside Tests},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {26},
number = {3},
pages = {23:1--23:15},
year = {2021},
url = {https://doi.org/10.1145/3441282},
doi = {10.1145/3441282},
timestamp = {Tue, 16 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/Pomeranz21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/Pomeranz21a,
author = {Irith Pomeranz},
title = {Equivalent Faults under Launch-on-Shift {(LOS)} Tests with Equal Primary
Input Vectors},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {26},
number = {4},
pages = {25:1--25:15},
year = {2021},
url = {https://doi.org/10.1145/3440013},
doi = {10.1145/3440013},
timestamp = {Wed, 12 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/Pomeranz21a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz21,
author = {Irith Pomeranz},
title = {Partitioning Functional Test Sequences Into Multicycle Functional
Broadside Tests},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {1},
pages = {89--99},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3029729},
doi = {10.1109/TVLSI.2020.3029729},
timestamp = {Thu, 11 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz21a,
author = {Irith Pomeranz},
title = {Test Compaction by Backward and Forward Extension of Multicycle Tests},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {1},
pages = {242--246},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3028005},
doi = {10.1109/TVLSI.2020.3028005},
timestamp = {Thu, 11 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz21a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PomeranzL21,
author = {Irith Pomeranz and
Xijiang Lin},
title = {Single Test Type to Replace Broadside and Skewed-Load Tests for Transition
Faults},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {2},
pages = {423--433},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3038368},
doi = {10.1109/TVLSI.2020.3038368},
timestamp = {Thu, 11 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PomeranzL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz21b,
author = {Irith Pomeranz},
title = {Functional Constraints in the Selection of Two-Cycle Gate-Exhaustive
Faults for Test Generation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {7},
pages = {1500--1504},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3081046},
doi = {10.1109/TVLSI.2021.3081046},
timestamp = {Tue, 13 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz21b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/Pomeranz21,
author = {Irith Pomeranz},
title = {Positive and Negative Extra Clocking of {LFSR} Seeds for Reduced Numbers
of Stored Tests},
booktitle = {30th {IEEE} Asian Test Symposium, {ATS} 2021, Matsuyama, Ehime, Japan,
November 22-25, 2021},
pages = {109--114},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ATS52891.2021.00031},
doi = {10.1109/ATS52891.2021.00031},
timestamp = {Mon, 17 Jan 2022 16:24:22 +0100},
biburl = {https://dblp.org/rec/conf/ats/Pomeranz21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/Pomeranz21,
author = {Irith Pomeranz},
editor = {Luigi Dilillo and
Luca Cassano and
Athanasios Papadimitriou},
title = {Zoom-In Feature for Storage-Based Logic Built-In Self-Test},
booktitle = {36th {IEEE} International Symposium on Defect and Fault Tolerance
in {VLSI} and Nanotechnology Systems, {DFT} 2021, Athens, Greece,
October 6-8, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/DFT52944.2021.9568357},
doi = {10.1109/DFT52944.2021.9568357},
timestamp = {Fri, 22 Oct 2021 15:23:35 +0200},
biburl = {https://dblp.org/rec/conf/dft/Pomeranz21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/Pomeranz21,
author = {Irith Pomeranz},
title = {Compact Set of {LFSR} Seeds for Diagnostic Tests},
booktitle = {39th {IEEE} {VLSI} Test Symposium, {VTS} 2021, San Diego, CA, USA,
April 25-28, 2021},
pages = {1--7},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VTS50974.2021.9441041},
doi = {10.1109/VTS50974.2021.9441041},
timestamp = {Wed, 09 Jun 2021 08:59:55 +0200},
biburl = {https://dblp.org/rec/conf/vts/Pomeranz21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/Pomeranz20,
author = {Irith Pomeranz},
title = {LFSR-based generation of boundary-functional broadside tests},
journal = {{IET} Comput. Digit. Tech.},
volume = {14},
number = {2},
pages = {61--68},
year = {2020},
url = {https://doi.org/10.1049/iet-cdt.2019.0058},
doi = {10.1049/IET-CDT.2019.0058},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/Pomeranz20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz20,
author = {Irith Pomeranz},
title = {Multicycle Broadside and Skewed-Load Tests for Test Compaction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {39},
number = {1},
pages = {262--266},
year = {2020},
url = {https://doi.org/10.1109/TCAD.2018.2887049},
doi = {10.1109/TCAD.2018.2887049},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz20a,
author = {Irith Pomeranz},
title = {Reverse Low-Power Broadside Tests},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {39},
number = {3},
pages = {742--746},
year = {2020},
url = {https://doi.org/10.1109/TCAD.2019.2894675},
doi = {10.1109/TCAD.2019.2894675},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz20a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz20b,
author = {Irith Pomeranz},
title = {Switching Activity of Faulty Circuits in Presence of Multiple Transition
Faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {39},
number = {4},
pages = {936--945},
year = {2020},
url = {https://doi.org/10.1109/TCAD.2019.2902326},
doi = {10.1109/TCAD.2019.2902326},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz20b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz20c,
author = {Irith Pomeranz},
title = {Broadside Tests for Transition and Stuck-At Faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {39},
number = {8},
pages = {1739--1743},
year = {2020},
url = {https://doi.org/10.1109/TCAD.2019.2935046},
doi = {10.1109/TCAD.2019.2935046},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz20c.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz20d,
author = {Irith Pomeranz},
title = {Globally Functional Transparent-Scan Sequences},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {39},
number = {10},
pages = {3012--3022},
year = {2020},
url = {https://doi.org/10.1109/TCAD.2019.2939331},
doi = {10.1109/TCAD.2019.2939331},
timestamp = {Tue, 06 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz20d.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz20e,
author = {Irith Pomeranz},
title = {New Targets for Diagnostic Test Generation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {39},
number = {10},
pages = {3035--3043},
year = {2020},
url = {https://doi.org/10.1109/TCAD.2019.2928971},
doi = {10.1109/TCAD.2019.2928971},
timestamp = {Tue, 06 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz20e.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz20f,
author = {Irith Pomeranz},
title = {Functional Broadside Tests Under Broadcast Scan},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {39},
number = {10},
pages = {3139--3143},
year = {2020},
url = {https://doi.org/10.1109/TCAD.2019.2939324},
doi = {10.1109/TCAD.2019.2939324},
timestamp = {Tue, 06 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz20f.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz20g,
author = {Irith Pomeranz},
title = {Direct Computation of LFSR-Based Stored Tests for Broadside and Skewed-Load
Tests},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {39},
number = {12},
pages = {5238--5246},
year = {2020},
url = {https://doi.org/10.1109/TCAD.2020.2966452},
doi = {10.1109/TCAD.2020.2966452},
timestamp = {Tue, 01 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz20g.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzV20,
author = {Irith Pomeranz and
Srikanth Venkataraman},
title = {LFSR-Based Test Generation for Reduced Fail Data Volume},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {39},
number = {12},
pages = {5261--5266},
year = {2020},
url = {https://doi.org/10.1109/TCAD.2020.2971527},
doi = {10.1109/TCAD.2020.2971527},
timestamp = {Tue, 01 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzV20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/Pomeranz20,
author = {Irith Pomeranz},
title = {Target Faults for Test Compaction Based on Multicycle Tests},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {25},
number = {2},
pages = {18:1--18:14},
year = {2020},
url = {https://doi.org/10.1145/3375278},
doi = {10.1145/3375278},
timestamp = {Wed, 01 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/Pomeranz20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz20,
author = {Irith Pomeranz},
title = {Selection of Primary Output Vectors to Observe Under Multicycle Tests},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {1},
pages = {156--162},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2941883},
doi = {10.1109/TVLSI.2019.2941883},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz20a,
author = {Irith Pomeranz},
title = {Extra Clocking of {LFSR} Seeds for Improved Path Delay Fault Coverage},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {2},
pages = {544--552},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2947340},
doi = {10.1109/TVLSI.2019.2947340},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz20a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz20b,
author = {Irith Pomeranz},
title = {{RETRO:} Reintroducing Tests for Improved Reverse Order Fault Simulation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {8},
pages = {1930--1934},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2997762},
doi = {10.1109/TVLSI.2020.2997762},
timestamp = {Wed, 26 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz20b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz20c,
author = {Irith Pomeranz},
title = {Broad-Brush Compaction for Sequential Test Generation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {8},
pages = {1940--1944},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2992097},
doi = {10.1109/TVLSI.2020.2992097},
timestamp = {Wed, 26 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz20c.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/Pomeranz20,
author = {Irith Pomeranz},
editor = {Luigi Dilillo and
Mihalis Psarakis and
Taniya Siddiqua},
title = {Improving a Test Set to Cover Test Holes by Detecting Gate-Exhaustive
Faults},
booktitle = {{IEEE} International Symposium on Defect and Fault Tolerance in {VLSI}
and Nanotechnology Systems, {DFT} 2020, Frascati, Italy, October 19-21,
2020},
pages = {1--4},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/DFT50435.2020.9250778},
doi = {10.1109/DFT50435.2020.9250778},
timestamp = {Tue, 17 Nov 2020 13:54:22 +0100},
biburl = {https://dblp.org/rec/conf/dft/Pomeranz20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iolts/Pomeranz20,
author = {Irith Pomeranz},
title = {Storage Based Built-In Test Pattern Generation Method for Close-to-Functional
Broadside Tests},
booktitle = {26th {IEEE} International Symposium on On-Line Testing and Robust
System Design, {IOLTS} 2020, Napoli, Italy, July 13-15, 2020},
pages = {1--4},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/IOLTS50870.2020.9159705},
doi = {10.1109/IOLTS50870.2020.9159705},
timestamp = {Mon, 10 Aug 2020 17:49:57 +0200},
biburl = {https://dblp.org/rec/conf/iolts/Pomeranz20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iolts/PomeranzK20,
author = {Irith Pomeranz and
Sandip Kundu},
title = {Reduced Fault Coverage as a Target for Design Scaffolding Security},
booktitle = {26th {IEEE} International Symposium on On-Line Testing and Robust
System Design, {IOLTS} 2020, Napoli, Italy, July 13-15, 2020},
pages = {1--6},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/IOLTS50870.2020.9159706},
doi = {10.1109/IOLTS50870.2020.9159706},
timestamp = {Mon, 10 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iolts/PomeranzK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/Pomeranz20,
author = {Irith Pomeranz},
title = {Selecting Close-to-Functional Path Delay Faults for Test Generation},
booktitle = {{IEEE} International Test Conference, {ITC} 2020, Washington, DC,
USA, November 1-6, 2020},
pages = {1--5},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ITC44778.2020.9325255},
doi = {10.1109/ITC44778.2020.9325255},
timestamp = {Mon, 25 Jan 2021 08:44:58 +0100},
biburl = {https://dblp.org/rec/conf/itc/Pomeranz20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/Pomeranz20,
author = {Irith Pomeranz},
title = {Input Test Data Volume Reduction Using Seed Complementation and Multiple
LFSRs},
booktitle = {38th {IEEE} {VLSI} Test Symposium, {VTS} 2020, San Diego, CA, USA,
April 5-8, 2020},
pages = {1--6},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VTS48691.2020.9107617},
doi = {10.1109/VTS48691.2020.9107617},
timestamp = {Thu, 25 Jun 2020 15:32:49 +0200},
biburl = {https://dblp.org/rec/conf/vts/Pomeranz20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/Pomeranz20a,
author = {Irith Pomeranz},
title = {Non-Masking Non-Robust Tests for Path Delay Faults},
booktitle = {38th {IEEE} {VLSI} Test Symposium, {VTS} 2020, San Diego, CA, USA,
April 5-8, 2020},
pages = {1--6},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VTS48691.2020.9107556},
doi = {10.1109/VTS48691.2020.9107556},
timestamp = {Thu, 25 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vts/Pomeranz20a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/Pomeranz19,
author = {Irith Pomeranz},
title = {Updating the sets of target faults during test generation for multiple
fault models},
journal = {{IET} Comput. Digit. Tech.},
volume = {13},
number = {5},
pages = {369--375},
year = {2019},
url = {https://doi.org/10.1049/iet-cdt.2018.5111},
doi = {10.1049/IET-CDT.2018.5111},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/Pomeranz19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz19,
author = {Irith Pomeranz},
title = {Diagnostic Test Generation That Addresses Diagnostic Holes},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {2},
pages = {335--344},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2812121},
doi = {10.1109/TCAD.2018.2812121},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz19a,
author = {Irith Pomeranz},
title = {LFSR-Based Test Generation for Path Delay Faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {2},
pages = {345--353},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2812120},
doi = {10.1109/TCAD.2018.2812120},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz19a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz19b,
author = {Irith Pomeranz},
title = {Skewed-Load Tests for Transition and Stuck-at Faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {10},
pages = {1969--1973},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2873233},
doi = {10.1109/TCAD.2018.2873233},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz19b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz19c,
author = {Irith Pomeranz},
title = {Invisible-Scan: {A} Design-for-Testability Approach for Functional
Test Sequences},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {38},
number = {12},
pages = {2357--2365},
year = {2019},
url = {https://doi.org/10.1109/TCAD.2018.2878176},
doi = {10.1109/TCAD.2018.2878176},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz19c.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/Pomeranz19,
author = {Irith Pomeranz},
title = {Boundary-Functional Broadside and Skewed-Load Tests},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {24},
number = {1},
pages = {7:1--7:20},
year = {2019},
url = {https://doi.org/10.1145/3276976},
doi = {10.1145/3276976},
timestamp = {Fri, 10 May 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/Pomeranz19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/Pomeranz19a,
author = {Irith Pomeranz},
title = {Incomplete Tests for Undetectable Faults to Improve Test Set Quality},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {24},
number = {2},
pages = {23:1--23:13},
year = {2019},
url = {https://doi.org/10.1145/3306493},
doi = {10.1145/3306493},
timestamp = {Fri, 10 May 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/Pomeranz19a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/WangPRSV19,
author = {Naixing Wang and
Irith Pomeranz and
Sudhakar M. Reddy and
Arani Sinha and
Srikanth Venkataraman},
title = {Layout Resynthesis by Applying Design-for-manufacturability Guidelines
to Avoid Low-coverage Areas of a Cell-based Design},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {24},
number = {4},
pages = {42:1--42:19},
year = {2019},
url = {https://doi.org/10.1145/3325066},
doi = {10.1145/3325066},
timestamp = {Wed, 07 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/WangPRSV19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz19,
author = {Irith Pomeranz},
title = {Test Compaction by Test Removal Under Transparent Scan},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {2},
pages = {496--500},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2878067},
doi = {10.1109/TVLSI.2018.2878067},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz19a,
author = {Irith Pomeranz},
title = {Extracting a Close-to-Minimum Multicycle Functional Broadside Test
Set From a Functional Test Sequence},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {6},
pages = {1428--1437},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2895386},
doi = {10.1109/TVLSI.2019.2895386},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz19a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz19b,
author = {Irith Pomeranz},
title = {Test Scores for Improving the Accuracy of Logic Diagnosis for Multiple
Defects},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {7},
pages = {1720--1724},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2900836},
doi = {10.1109/TVLSI.2019.2900836},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz19b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz19c,
author = {Irith Pomeranz},
title = {Extended Transparent-Scan},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {9},
pages = {2096--2104},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2916497},
doi = {10.1109/TVLSI.2019.2916497},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz19c.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz19d,
author = {Irith Pomeranz},
title = {Padding of Multicycle Broadside and Skewed-Load Tests},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {11},
pages = {2587--2595},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2924319},
doi = {10.1109/TVLSI.2019.2924319},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz19d.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/WangWTCLKP19,
author = {Naixing Wang and
Chen Wang and
Kun{-}Han Tsai and
Wu{-}Tung Cheng and
Xijiang Lin and
Mark Kassab and
Irith Pomeranz},
title = {{TEA:} {A} Test Generation Algorithm for Designs with Timing Exceptions},
booktitle = {28th {IEEE} Asian Test Symposium, {ATS} 2019, Kolkata, India, December
10-13, 2019},
pages = {19--24},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ATS47505.2019.000-6},
doi = {10.1109/ATS47505.2019.000-6},
timestamp = {Wed, 22 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ats/WangWTCLKP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/WangPRSV19,
author = {Naixing Wang and
Irith Pomeranz and
Sudhakar M. Reddy and
Arani Sinha and
Srikanth Venkataraman},
editor = {J{\"{u}}rgen Teich and
Franco Fummi},
title = {Resynthesis for Avoiding Undetectable Faults Based on Design-for-Manufacturability
Guidelines},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2019, Florence, Italy, March 25-29, 2019},
pages = {1022--1027},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/DATE.2019.8715037},
doi = {10.23919/DATE.2019.8715037},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/WangPRSV19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/Pomeranz19,
author = {Irith Pomeranz},
title = {Iterative Test Generation for Gate-Exhaustive Faults to Cover the
Sites of Undetectable Target Faults},
booktitle = {{IEEE} International Test Conference, {ITC} 2019, Washington, DC,
USA, November 9-15, 2019},
pages = {1--7},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ITC44170.2019.9000124},
doi = {10.1109/ITC44170.2019.9000124},
timestamp = {Mon, 24 Feb 2020 17:28:46 +0100},
biburl = {https://dblp.org/rec/conf/itc/Pomeranz19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/Pomeranz19a,
author = {Irith Pomeranz},
title = {Compaction of a Functional Broadside Test Set through the Compaction
of a Functional Test Sequence without Sequential Fault Simulation},
booktitle = {{IEEE} International Test Conference, {ITC} 2019, Washington, DC,
USA, November 9-15, 2019},
pages = {1--7},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ITC44170.2019.9000161},
doi = {10.1109/ITC44170.2019.9000161},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/Pomeranz19a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/Pomeranz19,
author = {Irith Pomeranz},
title = {Test Compaction Under Bounded Transparent-Scan},
booktitle = {37th {IEEE} {VLSI} Test Symposium, {VTS} 2019, Monterey, CA, USA,
April 23-25, 2019},
pages = {1--6},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VTS.2019.8758644},
doi = {10.1109/VTS.2019.8758644},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/vts/Pomeranz19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/PomeranzCV19,
author = {Irith Pomeranz and
Vivek Chickermane and
Srikanth Venkataraman},
title = {Observation Point Placement for Improved Logic Diagnosis based on
Large Sets of Candidate Faults},
booktitle = {37th {IEEE} {VLSI} Test Symposium, {VTS} 2019, Monterey, CA, USA,
April 23-25, 2019},
pages = {1--6},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VTS.2019.8758663},
doi = {10.1109/VTS.2019.8758663},
timestamp = {Mon, 15 Jul 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vts/PomeranzCV19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/Pomeranz18,
author = {Irith Pomeranz},
title = {On-chip generation of primary input sequences for multicycle functional
broadside tests},
journal = {{IET} Comput. Digit. Tech.},
volume = {12},
number = {3},
pages = {80--86},
year = {2018},
url = {https://doi.org/10.1049/iet-cdt.2017.0032},
doi = {10.1049/IET-CDT.2017.0032},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/Pomeranz18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/Pomeranz18a,
author = {Irith Pomeranz},
title = {Static test compaction procedure for large pools of multicycle functional
broadside tests},
journal = {{IET} Comput. Digit. Tech.},
volume = {12},
number = {5},
pages = {233--240},
year = {2018},
url = {https://doi.org/10.1049/iet-cdt.2017.0239},
doi = {10.1049/IET-CDT.2017.0239},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/Pomeranz18a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz18,
author = {Irith Pomeranz},
title = {Improving the Diagnosability of Scan Chain Faults Under Transparent-Scan
by Observation Points},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {6},
pages = {1278--1287},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2748020},
doi = {10.1109/TCAD.2017.2748020},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz18a,
author = {Irith Pomeranz},
title = {An Initialization Process to Support Online Testing Based on Output
Comparison for Identical Finite-State Machines},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {7},
pages = {1494--1504},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2750060},
doi = {10.1109/TCAD.2017.2750060},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz18a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz18b,
author = {Irith Pomeranz},
title = {Autonomous Multicycle Tests With Low Storage and Test Application
Time Overheads},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {9},
pages = {1881--1892},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2774269},
doi = {10.1109/TCAD.2017.2774269},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz18b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/Pomeranz18,
author = {Irith Pomeranz},
title = {Partially Invariant Patterns for \emph{LFSR}-Based Generation of Close-to-Functional
Broadside Tests},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {23},
number = {4},
pages = {53:1--53:18},
year = {2018},
url = {https://doi.org/10.1145/3201405},
doi = {10.1145/3201405},
timestamp = {Wed, 21 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/Pomeranz18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/Pomeranz18a,
author = {Irith Pomeranz},
title = {Dynamically Determined Preferred Values and a Design-for-Testability
Approach for Multiplexer Select Inputs under Functional Test Sequences},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {23},
number = {5},
pages = {59:1--59:16},
year = {2018},
url = {https://doi.org/10.1145/3219778},
doi = {10.1145/3219778},
timestamp = {Wed, 21 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/Pomeranz18a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz18,
author = {Irith Pomeranz},
title = {Selecting Functional Test Sequences for Defect Diagnosis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {10},
pages = {2160--2164},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2849972},
doi = {10.1109/TVLSI.2018.2849972},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz18a,
author = {Irith Pomeranz},
title = {Observation Points on State Variables for the Compaction of Multicycle
Tests},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {11},
pages = {2567--2571},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2854704},
doi = {10.1109/TVLSI.2018.2854704},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz18a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/Pomeranz18,
author = {Irith Pomeranz},
title = {Postprocessing Procedure for Reducing the Faulty Switching Activity
of a Low-Power Test Set},
booktitle = {2018 {IEEE} International Symposium on Defect and Fault Tolerance
in {VLSI} and Nanotechnology Systems, {DFT} 2018, Chicago, IL, USA,
October 8-10, 2018},
pages = {1--6},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/DFT.2018.8602967},
doi = {10.1109/DFT.2018.8602967},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dft/Pomeranz18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/WangPBEV18,
author = {Naixing Wang and
Irith Pomeranz and
Brady Benware and
M. Enamul Amyeen and
Srikanth Venkataraman},
title = {Improving the Resolution of Multiple Defect Diagnosis by Removing
and Selecting Tests},
booktitle = {2018 {IEEE} International Symposium on Defect and Fault Tolerance
in {VLSI} and Nanotechnology Systems, {DFT} 2018, Chicago, IL, USA,
October 8-10, 2018},
pages = {1--6},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/DFT.2018.8602935},
doi = {10.1109/DFT.2018.8602935},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dft/WangPBEV18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ets/Pomeranz18,
author = {Irith Pomeranz},
title = {Covering undetected transition fault sites with optimistic unspecified
transition faults under multicycle tests},
booktitle = {23rd {IEEE} European Test Symposium, {ETS} 2018, Bremen, Germany,
May 28 - June 1, 2018},
pages = {1--2},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ETS.2018.8400704},
doi = {10.1109/ETS.2018.8400704},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/ets/Pomeranz18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ets/PomeranzV18,
author = {Irith Pomeranz and
Srikanth Venkataraman},
title = {Interconnect-aware tests to complement gate-exhaustive tests},
booktitle = {23rd {IEEE} European Test Symposium, {ETS} 2018, Bremen, Germany,
May 28 - June 1, 2018},
pages = {1--6},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ETS.2018.8400699},
doi = {10.1109/ETS.2018.8400699},
timestamp = {Fri, 06 Jul 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ets/PomeranzV18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/Pomeranz18,
author = {Irith Pomeranz},
title = {On Close-to-Functional Test Sequences},
booktitle = {{IEEE} International Test Conference, {ITC} 2018, Phoenix, AZ, USA,
October 29 - Nov. 1, 2018},
pages = {1--8},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/TEST.2018.8624703},
doi = {10.1109/TEST.2018.8624703},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/itc/Pomeranz18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/Pomeranz17,
author = {Irith Pomeranz},
title = {Reconstruction of a functional test sequence for increased fault coverage},
journal = {{IET} Comput. Digit. Tech.},
volume = {11},
number = {3},
pages = {91--97},
year = {2017},
url = {https://doi.org/10.1049/iet-cdt.2016.0107},
doi = {10.1049/IET-CDT.2016.0107},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/Pomeranz17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/Pomeranz17a,
author = {Irith Pomeranz},
title = {Metric for the ability of functional capture cycles to ensure functional
operation conditions},
journal = {{IET} Comput. Digit. Tech.},
volume = {11},
number = {3},
pages = {100--106},
year = {2017},
url = {https://doi.org/10.1049/iet-cdt.2016.0090},
doi = {10.1049/IET-CDT.2016.0090},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/Pomeranz17a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/GaudesiPRS17,
author = {Marco Gaudesi and
Irith Pomeranz and
Matteo Sonza Reorda and
Giovanni Squillero},
title = {New Techniques to Reduce the Execution Time of Functional Test Programs},
journal = {{IEEE} Trans. Computers},
volume = {66},
number = {7},
pages = {1268--1273},
year = {2017},
url = {https://doi.org/10.1109/TC.2016.2643663},
doi = {10.1109/TC.2016.2643663},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/GaudesiPRS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz17,
author = {Irith Pomeranz},
title = {Sequential Test Generation Based on Preferred Primary Input Cubes},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {36},
number = {2},
pages = {351--355},
year = {2017},
url = {https://doi.org/10.1109/TCAD.2016.2568210},
doi = {10.1109/TCAD.2016.2568210},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz17a,
author = {Irith Pomeranz},
title = {LFSR-Based Generation of Multicycle Tests},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {36},
number = {3},
pages = {503--507},
year = {2017},
url = {https://doi.org/10.1109/TCAD.2016.2587687},
doi = {10.1109/TCAD.2016.2587687},
timestamp = {Fri, 21 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz17a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz17b,
author = {Irith Pomeranz},
title = {Identifying Biases of a Defect Diagnosis Procedure},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {36},
number = {7},
pages = {1215--1225},
year = {2017},
url = {https://doi.org/10.1109/TCAD.2016.2618859},
doi = {10.1109/TCAD.2016.2618859},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz17b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz17c,
author = {Irith Pomeranz},
title = {Clock Sequences for Increasing the Fault Coverage of Functional Test
Sequences},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {36},
number = {7},
pages = {1231--1235},
year = {2017},
url = {https://doi.org/10.1109/TCAD.2016.2622622},
doi = {10.1109/TCAD.2016.2622622},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz17c.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz17d,
author = {Irith Pomeranz},
title = {Restoration-Based Merging of Functional Test Sequences},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {36},
number = {10},
pages = {1739--1749},
year = {2017},
url = {https://doi.org/10.1109/TCAD.2016.2638444},
doi = {10.1109/TCAD.2016.2638444},
timestamp = {Tue, 16 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz17d.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz17e,
author = {Irith Pomeranz},
title = {Close-to-Functional Broadside Tests With a Safety Margin},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {36},
number = {12},
pages = {2139--2143},
year = {2017},
url = {https://doi.org/10.1109/TCAD.2017.2669862},
doi = {10.1109/TCAD.2017.2669862},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz17e.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/Pomeranz17,
author = {Irith Pomeranz},
title = {Computation of Seeds for \emph{LFSR}-Based \emph{n}-Detection Test
Generation},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {22},
number = {2},
pages = {29:1--29:13},
year = {2017},
url = {https://doi.org/10.1145/2994144},
doi = {10.1145/2994144},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/Pomeranz17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/Pomeranz17a,
author = {Irith Pomeranz},
title = {Generation of Transparent-Scan Sequences for Diagnosis of Scan Chain
Faults},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {22},
number = {3},
pages = {43:1--43:17},
year = {2017},
url = {https://doi.org/10.1145/3007207},
doi = {10.1145/3007207},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/Pomeranz17a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/PomeranzAV17,
author = {Irith Pomeranz and
M. Enamul Amyeen and
Srikanth Venkataraman},
title = {Test Modification for Reduced Volumes of Fail Data},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {22},
number = {4},
pages = {67:1--67:17},
year = {2017},
url = {https://doi.org/10.1145/3065925},
doi = {10.1145/3065925},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/PomeranzAV17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BodhePAV17,
author = {Shraddha Bodhe and
Irith Pomeranz and
M. Enamul Amyeen and
Srikanth Venkataraman},
title = {Reordering Tests for Efficient Fail Data Collection and Tester Time
Reduction},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {4},
pages = {1497--1505},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2628321},
doi = {10.1109/TVLSI.2016.2628321},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BodhePAV17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz17,
author = {Irith Pomeranz},
title = {Selecting Replacements for Undetectable Path Delay Faults},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {6},
pages = {1988--1992},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2670147},
doi = {10.1109/TVLSI.2017.2670147},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/Pomeranz17,
author = {Irith Pomeranz},
title = {Test Compaction with Dynamic Updating of Faults for Coverage of Undetected
Transition Fault Sites},
booktitle = {26th {IEEE} Asian Test Symposium, {ATS} 2017, Taipei City, Taiwan,
November 27-30, 2017},
pages = {34--39},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/ATS.2017.19},
doi = {10.1109/ATS.2017.19},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/Pomeranz17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/Pomeranz17a,
author = {Irith Pomeranz},
title = {Compaction of a Transparent-Scan Sequence to Reduce the Fail Data
Volume for Scan Chain Faults},
booktitle = {26th {IEEE} Asian Test Symposium, {ATS} 2017, Taipei City, Taiwan,
November 27-30, 2017},
pages = {133--138},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/ATS.2017.35},
doi = {10.1109/ATS.2017.35},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/Pomeranz17a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/Pomeranz17,
author = {Irith Pomeranz},
editor = {David Atienza and
Giorgio Di Natale},
title = {A bridging fault model for line coverage in the presence of undetected
transition faults},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2017, Lausanne, Switzerland, March 27-31, 2017},
pages = {938--941},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.23919/DATE.2017.7927125},
doi = {10.23919/DATE.2017.7927125},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/Pomeranz17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/WangYLP17,
author = {Naixing Wang and
Bo Yao and
Xijiang Lin and
Irith Pomeranz},
title = {Functional Broadside Test Generation Using a Commercial {ATPG} Tool},
booktitle = {2017 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2017,
Bochum, Germany, July 3-5, 2017},
pages = {308--313},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/ISVLSI.2017.61},
doi = {10.1109/ISVLSI.2017.61},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/WangYLP17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/Pomeranz17,
author = {Irith Pomeranz},
title = {Static Compaction by Merging of Seeds for LFSR-Based Test Generation},
booktitle = {2017 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2017,
Bochum, Germany, July 3-5, 2017},
pages = {314--319},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/ISVLSI.2017.62},
doi = {10.1109/ISVLSI.2017.62},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/Pomeranz17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/Pomeranz17,
author = {Irith Pomeranz},
title = {Selecting target bridging faults for uniform circuit coverage},
booktitle = {{IEEE} International Test Conference, {ITC} 2017, Fort Worth, TX,
USA, October 31 - Nov. 2, 2017},
pages = {1--7},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/TEST.2017.8242061},
doi = {10.1109/TEST.2017.8242061},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/itc/Pomeranz17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/Pomeranz17a,
author = {Irith Pomeranz},
title = {{POSTT:} Path-oriented static test compaction for transition faults
in scan circuits},
booktitle = {{IEEE} International Test Conference, {ITC} 2017, Fort Worth, TX,
USA, October 31 - Nov. 2, 2017},
pages = {1--8},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/TEST.2017.8242073},
doi = {10.1109/TEST.2017.8242073},
timestamp = {Fri, 05 Jan 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/Pomeranz17a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/VenkataramanPBA17,
author = {Srikanth Venkataraman and
Irith Pomeranz and
Shraddha Bodhe and
M. Enamul Amyeen},
title = {Test reordering for improved scan chain diagnosis using an enhanced
defect diagnosis procedure},
booktitle = {{IEEE} International Test Conference, {ITC} 2017, Fort Worth, TX,
USA, October 31 - Nov. 2, 2017},
pages = {1--9},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/TEST.2017.8242049},
doi = {10.1109/TEST.2017.8242049},
timestamp = {Fri, 05 Jan 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/VenkataramanPBA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/Pomeranz17,
author = {Irith Pomeranz},
title = {Fail data reduction for diagnosis of scan chain faults under transparent-scan},
booktitle = {35th {IEEE} {VLSI} Test Symposium, {VTS} 2017, Las Vegas, NV, USA,
April 9-12, 2017},
pages = {1--6},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/VTS.2017.7928924},
doi = {10.1109/VTS.2017.7928924},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/Pomeranz17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/Pomeranz17a,
author = {Irith Pomeranz},
title = {Using piecewise-functional broadside tests for functional broadside
test compaction},
booktitle = {35th {IEEE} {VLSI} Test Symposium, {VTS} 2017, Las Vegas, NV, USA,
April 9-12, 2017},
pages = {1--6},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/VTS.2017.7928944},
doi = {10.1109/VTS.2017.7928944},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/Pomeranz17a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/Pomeranz16,
author = {Irith Pomeranz},
title = {Static test compaction for circuits with multiple independent scan
chains},
journal = {{IET} Comput. Digit. Tech.},
volume = {10},
number = {1},
pages = {12--17},
year = {2016},
url = {https://doi.org/10.1049/iet-cdt.2014.0191},
doi = {10.1049/IET-CDT.2014.0191},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/Pomeranz16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/Pomeranz16a,
author = {Irith Pomeranz},
title = {Improving the accuracy of defect diagnosis by adding and removing
tests},
journal = {{IET} Comput. Digit. Tech.},
volume = {10},
number = {2},
pages = {47--53},
year = {2016},
url = {https://doi.org/10.1049/iet-cdt.2015.0072},
doi = {10.1049/IET-CDT.2015.0072},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/Pomeranz16a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/Pomeranz16b,
author = {Irith Pomeranz},
title = {Combined input test data volume reduction for mixed broadside and
skewed-load test sets},
journal = {{IET} Comput. Digit. Tech.},
volume = {10},
number = {3},
pages = {138--145},
year = {2016},
url = {https://doi.org/10.1049/iet-cdt.2015.0117},
doi = {10.1049/IET-CDT.2015.0117},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/Pomeranz16b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/Pomeranz16,
author = {Irith Pomeranz},
title = {Improving the Accuracy of Defect Diagnosis with Multiple Sets of Candidate
Faults},
journal = {{IEEE} Trans. Computers},
volume = {65},
number = {7},
pages = {2332--2338},
year = {2016},
url = {https://doi.org/10.1109/TC.2015.2468234},
doi = {10.1109/TC.2015.2468234},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/Pomeranz16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/Pomeranz16a,
author = {Irith Pomeranz},
title = {LFSR-Based Generation of Partially-Functional Broadside Tests},
journal = {{IEEE} Trans. Computers},
volume = {65},
number = {8},
pages = {2659--2664},
year = {2016},
url = {https://doi.org/10.1109/TC.2015.2488621},
doi = {10.1109/TC.2015.2488621},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/Pomeranz16a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz16,
author = {Irith Pomeranz},
title = {Balancing the Numbers of Detected Faults for Improved Test Set Quality},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {35},
number = {2},
pages = {337--341},
year = {2016},
url = {https://doi.org/10.1109/TCAD.2015.2460463},
doi = {10.1109/TCAD.2015.2460463},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz16a,
author = {Irith Pomeranz},
title = {Static Test Compaction for Functional Test Sequences With Restoration
of Functional Switching Activity},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {35},
number = {10},
pages = {1755--1762},
year = {2016},
url = {https://doi.org/10.1109/TCAD.2015.2512931},
doi = {10.1109/TCAD.2015.2512931},
timestamp = {Tue, 16 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz16a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/Pomeranz16,
author = {Irith Pomeranz},
title = {Design-for-Testability for Functional Broadside Tests under Primary
Input Constraints},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {21},
number = {2},
pages = {35:1--35:18},
year = {2016},
url = {https://doi.org/10.1145/2831231},
doi = {10.1145/2831231},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/Pomeranz16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/Pomeranz16a,
author = {Irith Pomeranz},
title = {\emph{N}-Detection Test Sets for Circuits with Multiple Independent
Scan Chains},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {21},
number = {4},
pages = {68:1--68:15},
year = {2016},
url = {https://doi.org/10.1145/2897514},
doi = {10.1145/2897514},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/Pomeranz16a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/Pomeranz16b,
author = {Irith Pomeranz},
title = {Periodic Scan-In States to Reduce the Input Test Data Volume for Partially
Functional Broadside Tests},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {22},
number = {1},
pages = {7:1--7:22},
year = {2016},
url = {https://doi.org/10.1145/2911983},
doi = {10.1145/2911983},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/Pomeranz16b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BodheAPV16,
author = {Shraddha Bodhe and
M. Enamul Amyeen and
Irith Pomeranz and
Srikanth Venkataraman},
title = {Diagnostic Fail Data Minimization Using an N-Cover Algorithm},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {24},
number = {3},
pages = {1198--1202},
year = {2016},
url = {https://doi.org/10.1109/TVLSI.2015.2432717},
doi = {10.1109/TVLSI.2015.2432717},
timestamp = {Tue, 16 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BodheAPV16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz16,
author = {Irith Pomeranz},
title = {Computing Seeds for LFSR-Based Test Generation From Nontest Cubes},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {24},
number = {6},
pages = {2392--2396},
year = {2016},
url = {https://doi.org/10.1109/TVLSI.2015.2496190},
doi = {10.1109/TVLSI.2015.2496190},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz16a,
author = {Irith Pomeranz},
title = {A Test Selection Procedure for Improving the Accuracy of Defect Diagnosis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {24},
number = {8},
pages = {2759--2767},
year = {2016},
url = {https://doi.org/10.1109/TVLSI.2016.2533444},
doi = {10.1109/TVLSI.2016.2533444},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz16a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/PomeranzR16,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On the Switching Activity in Faulty Circuits During Test Application},
booktitle = {25th {IEEE} Asian Test Symposium, {ATS} 2016, Hiroshima, Japan, November
21-24, 2016},
pages = {13--18},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/ATS.2016.12},
doi = {10.1109/ATS.2016.12},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/PomeranzR16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/AmyeenPV16,
author = {M. Enamul Amyeen and
Irith Pomeranz and
Srikanth Venkataraman},
title = {A Joint Diagnostic Test Generation Procedure with Dynamic Test Compaction},
booktitle = {25th {IEEE} Asian Test Symposium, {ATS} 2016, Hiroshima, Japan, November
21-24, 2016},
pages = {138--143},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/ATS.2016.15},
doi = {10.1109/ATS.2016.15},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/AmyeenPV16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/Pomeranz16,
author = {Irith Pomeranz},
title = {A Compact Set of Seeds for LFSR-Based Test Generation from a Fully-Specified
Compact Test Set},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2016, Pittsburgh,
PA, USA, July 11-13, 2016},
pages = {361--366},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/ISVLSI.2016.20},
doi = {10.1109/ISVLSI.2016.20},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/Pomeranz16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/BodheAGMPV16,
author = {Shraddha Bodhe and
M. Enamul Amyeen and
Clariza Galendez and
Houston Mooers and
Irith Pomeranz and
Srikanth Venkataraman},
title = {Reduction of diagnostic fail data volume and tester time using a dynamic
N-cover algorithm},
booktitle = {34th {IEEE} {VLSI} Test Symposium, {VTS} 2016, Las Vegas, NV, USA,
April 25-27, 2016},
pages = {1--6},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/VTS.2016.7477280},
doi = {10.1109/VTS.2016.7477280},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/BodheAGMPV16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/Pomeranz16,
author = {Irith Pomeranz},
title = {A convergent procedure for partially-reachable states},
booktitle = {34th {IEEE} {VLSI} Test Symposium, {VTS} 2016, Las Vegas, NV, USA,
April 25-27, 2016},
pages = {1--6},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/VTS.2016.7477264},
doi = {10.1109/VTS.2016.7477264},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/Pomeranz16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/Pomeranz15,
author = {Irith Pomeranz},
title = {Use of input necessary assignments for test generation based on merging
of test cubes},
journal = {{IET} Comput. Digit. Tech.},
volume = {9},
number = {2},
pages = {106--112},
year = {2015},
url = {https://doi.org/10.1049/iet-cdt.2014.0009},
doi = {10.1049/IET-CDT.2014.0009},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/Pomeranz15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/Pomeranz15,
author = {Irith Pomeranz},
title = {Piecewise-Functional Broadside Tests Based on Reachable States},
journal = {{IEEE} Trans. Computers},
volume = {64},
number = {8},
pages = {2415--2420},
year = {2015},
url = {https://doi.org/10.1109/TC.2014.2360538},
doi = {10.1109/TC.2014.2360538},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/Pomeranz15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/Pomeranz15a,
author = {Irith Pomeranz},
title = {Two-Dimensional Static Test Compaction for Functional Test Sequences},
journal = {{IEEE} Trans. Computers},
volume = {64},
number = {10},
pages = {3009--3015},
year = {2015},
url = {https://doi.org/10.1109/TC.2014.2378285},
doi = {10.1109/TC.2014.2378285},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/Pomeranz15a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/Pomeranz15b,
author = {Irith Pomeranz},
title = {Test Vector Omission for Fault Coverage Improvement of Functional
Test Sequences},
journal = {{IEEE} Trans. Computers},
volume = {64},
number = {11},
pages = {3317--3321},
year = {2015},
url = {https://doi.org/10.1109/TC.2015.2395424},
doi = {10.1109/TC.2015.2395424},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/Pomeranz15b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz15,
author = {Irith Pomeranz},
title = {A Multicycle Test Set Based on a Two-Cycle Test Set With Constant
Primary Input Vectors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {34},
number = {7},
pages = {1124--1132},
year = {2015},
url = {https://doi.org/10.1109/TCAD.2015.2408257},
doi = {10.1109/TCAD.2015.2408257},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz15a,
author = {Irith Pomeranz},
title = {Computation of Seeds for LFSR-Based Diagnostic Test Generation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {34},
number = {12},
pages = {2004--2012},
year = {2015},
url = {https://doi.org/10.1109/TCAD.2015.2459031},
doi = {10.1109/TCAD.2015.2459031},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz15a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/Pomeranz15,
author = {Irith Pomeranz},
title = {A Generalized Definition of Unnecessary Test Vectors in Functional
Test Sequences},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {20},
number = {2},
pages = {29:1--29:13},
year = {2015},
url = {https://doi.org/10.1145/2699853},
doi = {10.1145/2699853},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/Pomeranz15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/Pomeranz15a,
author = {Irith Pomeranz},
title = {{FOLD:} Extreme Static Test Compaction by Folding of Functional Test
Sequences},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {20},
number = {4},
pages = {57:1--57:19},
year = {2015},
url = {https://doi.org/10.1145/2764455},
doi = {10.1145/2764455},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/Pomeranz15a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/Pomeranz15b,
author = {Irith Pomeranz},
title = {Enhanced Test Compaction for Multicycle Broadside Tests by Using State
Complementation},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {21},
number = {1},
pages = {13:1--13:20},
year = {2015},
url = {https://doi.org/10.1145/2778953},
doi = {10.1145/2778953},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/Pomeranz15b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz15,
author = {Irith Pomeranz},
title = {Skewed-Load Test Cubes Based on Functional Broadside Tests for a Low-Power
Test Set},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {23},
number = {3},
pages = {593--597},
year = {2015},
url = {https://doi.org/10.1109/TVLSI.2014.2311170},
doi = {10.1109/TVLSI.2014.2311170},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz15a,
author = {Irith Pomeranz},
title = {Static Test Compaction for Low-Power Test Sets by Increasing the Switching
Activity},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {23},
number = {9},
pages = {1936--1940},
year = {2015},
url = {https://doi.org/10.1109/TVLSI.2014.2345762},
doi = {10.1109/TVLSI.2014.2345762},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz15a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz15b,
author = {Irith Pomeranz},
title = {Modeling a Set of Functional Test Sequences as a Single Sequence for
Test Compaction},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {23},
number = {11},
pages = {2629--2638},
year = {2015},
url = {https://doi.org/10.1109/TVLSI.2014.2370751},
doi = {10.1109/TVLSI.2014.2370751},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz15b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz15c,
author = {Irith Pomeranz},
title = {Test Compaction by Sharing of Functional Test Sequences Among Logic
Blocks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {23},
number = {12},
pages = {3006--3014},
year = {2015},
url = {https://doi.org/10.1109/TVLSI.2014.2382609},
doi = {10.1109/TVLSI.2014.2382609},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz15c.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/Pomeranz15,
author = {Irith Pomeranz},
title = {Generation of close-to-functional broadside tests with equal primary
input vectors},
booktitle = {Proceedings of the 52nd Annual Design Automation Conference, San Francisco,
CA, USA, June 7-11, 2015},
pages = {137:1--137:6},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2744769.2744844},
doi = {10.1145/2744769.2744844},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/Pomeranz15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/Pomeranz15,
author = {Irith Pomeranz},
title = {Piecewise-functional broadside tests based on intersections of reachable
states},
booktitle = {2015 {IEEE} International Symposium on Defect and Fault Tolerance
in {VLSI} and Nanotechnology Systems, {DFTS} 2015, Amherst, MA, USA,
October 12-14, 2015},
pages = {133--138},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/DFT.2015.7315150},
doi = {10.1109/DFT.2015.7315150},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dft/Pomeranz15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ets/GaudesiRP15,
author = {Marco Gaudesi and
Matteo Sonza Reorda and
Irith Pomeranz},
title = {On test program compaction},
booktitle = {20th {IEEE} European Test Symposium, {ETS} 2015, Cluj-Napoca, Romania,
25-29 May, 2015},
pages = {1--6},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ETS.2015.7138771},
doi = {10.1109/ETS.2015.7138771},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/ets/GaudesiRP15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/NitinPV15,
author = {Nitin and
Irith Pomeranz and
T. N. Vijaykumar},
editor = {Deborah T. Marr and
David H. Albonesi},
title = {FaultHound: value-locality-based soft-fault tolerance},
booktitle = {Proceedings of the 42nd Annual International Symposium on Computer
Architecture, Portland, OR, USA, June 13-17, 2015},
pages = {668--681},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2749469.2750372},
doi = {10.1145/2749469.2750372},
timestamp = {Fri, 09 Jul 2021 15:51:20 +0200},
biburl = {https://dblp.org/rec/conf/isca/NitinPV15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/Pomeranz15,
author = {Irith Pomeranz},
title = {Reducing the Storage Requirements of a Set of Functional Test Sequences
by Using a Background Sequence},
booktitle = {2015 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2015,
Montpellier, France, July 8-10, 2015},
pages = {155--160},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/ISVLSI.2015.15},
doi = {10.1109/ISVLSI.2015.15},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/Pomeranz15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/Pomeranz15,
author = {Irith Pomeranz},
title = {Improving the accuracy of defect diagnosis by considering reduced
diagnostic information},
booktitle = {33rd {IEEE} {VLSI} Test Symposium, {VTS} 2015, Napa, CA, USA, April
27-29, 2015},
pages = {1--6},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/VTS.2015.7116270},
doi = {10.1109/VTS.2015.7116270},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/Pomeranz15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/Pomeranz15a,
author = {Irith Pomeranz},
title = {Test vector omission with minimal sets of simulated faults},
booktitle = {33rd {IEEE} {VLSI} Test Symposium, {VTS} 2015, Napa, CA, USA, April
27-29, 2015},
pages = {1--6},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/VTS.2015.7116297},
doi = {10.1109/VTS.2015.7116297},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/Pomeranz15a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/Pomeranz15b,
author = {Irith Pomeranz},
title = {Test compaction by test cube merging for four-way bridging faults},
booktitle = {33rd {IEEE} {VLSI} Test Symposium, {VTS} 2015, Napa, CA, USA, April
27-29, 2015},
pages = {1--6},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/VTS.2015.7116298},
doi = {10.1109/VTS.2015.7116298},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/Pomeranz15b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/Pomeranz15c,
author = {Irith Pomeranz},
title = {A definition of the number of detections for faults with single tests
in a compact scan-based test set},
booktitle = {33rd {IEEE} {VLSI} Test Symposium, {VTS} 2015, Napa, CA, USA, April
27-29, 2015},
pages = {1--6},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/VTS.2015.7116302},
doi = {10.1109/VTS.2015.7116302},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/Pomeranz15c.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/Pomeranz14,
author = {Irith Pomeranz},
title = {Reducing the input test data volume under transparent scan},
journal = {{IET} Comput. Digit. Tech.},
volume = {8},
number = {1},
pages = {1--10},
year = {2014},
url = {https://doi.org/10.1049/iet-cdt.2013.0067},
doi = {10.1049/IET-CDT.2013.0067},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/Pomeranz14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/Pomeranz14a,
author = {Irith Pomeranz},
title = {Multi-cycle broadside tests with runs of constant primary input vectors},
journal = {{IET} Comput. Digit. Tech.},
volume = {8},
number = {2},
pages = {90--96},
year = {2014},
url = {https://doi.org/10.1049/iet-cdt.2013.0101},
doi = {10.1049/IET-CDT.2013.0101},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/Pomeranz14a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/Pomeranz14,
author = {Irith Pomeranz},
title = {Sharing Logic for Built-In Generationof Functional Broadside Tests},
journal = {{IEEE} Trans. Computers},
volume = {63},
number = {4},
pages = {1048--1054},
year = {2014},
url = {https://doi.org/10.1109/TC.2013.69},
doi = {10.1109/TC.2013.69},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/Pomeranz14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz14,
author = {Irith Pomeranz},
title = {Unknown Output Values of Faulty Circuits and Output Response Compaction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {2},
pages = {323--327},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2284012},
doi = {10.1109/TCAD.2013.2284012},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz14a,
author = {Irith Pomeranz},
title = {Input Test Data Volume Reduction for Skewed-Load Tests by Additional
Shifting of Scan-In States},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {4},
pages = {638--642},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2290085},
doi = {10.1109/TCAD.2013.2290085},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz14a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz14b,
author = {Irith Pomeranz},
title = {Selection of Functional Test Sequences With Overlaps},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {7},
pages = {1095--1099},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2013.2293473},
doi = {10.1109/TCAD.2013.2293473},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz14b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz14c,
author = {Irith Pomeranz},
title = {Simultaneous Generation of Functional and Low-Power Non-Functional
Broadside Tests},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {8},
pages = {1245--1257},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2314293},
doi = {10.1109/TCAD.2014.2314293},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz14c.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz14d,
author = {Irith Pomeranz},
title = {Functional Broadside Tests for Multistep Defect Diagnosis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {9},
pages = {1429--1433},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2331559},
doi = {10.1109/TCAD.2014.2331559},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz14d.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz14e,
author = {Irith Pomeranz},
title = {Static Test Compaction for Scan Circuits by Using Restoration to Modify
and Remove Tests},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {12},
pages = {1955--1964},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2358932},
doi = {10.1109/TCAD.2014.2358932},
timestamp = {Tue, 16 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz14e.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz14f,
author = {Irith Pomeranz},
title = {Improving the Accuracy of Defect Diagnosis by Considering Fewer Tests},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {12},
pages = {2010--2014},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2358936},
doi = {10.1109/TCAD.2014.2358936},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz14f.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/Pomeranz14,
author = {Irith Pomeranz},
title = {Low-power skewed-load tests based on functional broadside tests},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {19},
number = {2},
pages = {18:1--18:18},
year = {2014},
url = {https://doi.org/10.1145/2566664},
doi = {10.1145/2566664},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/Pomeranz14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/Pomeranz14a,
author = {Irith Pomeranz},
title = {Design-for-testability for multi-cycle broadside tests by holding
of state variables},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {19},
number = {2},
pages = {19:1--19:20},
year = {2014},
url = {https://doi.org/10.1145/2566665},
doi = {10.1145/2566665},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/Pomeranz14a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz14,
author = {Irith Pomeranz},
title = {Restoration-Based Procedures With Set Covering Heuristics for Static
Test Compaction of Functional Test Sequences},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {22},
number = {4},
pages = {779--791},
year = {2014},
url = {https://doi.org/10.1109/TVLSI.2013.2253499},
doi = {10.1109/TVLSI.2013.2253499},
timestamp = {Tue, 16 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz14a,
author = {Irith Pomeranz},
title = {Test Compaction by Sharing of Transparent-Scan Sequences Among Logic
Blocks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {22},
number = {4},
pages = {792--802},
year = {2014},
url = {https://doi.org/10.1109/TVLSI.2013.2256438},
doi = {10.1109/TVLSI.2013.2256438},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz14a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz14b,
author = {Irith Pomeranz},
title = {Low-Power Test Generation by Merging of Functional Broadside Test
Cubes},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {22},
number = {7},
pages = {1570--1582},
year = {2014},
url = {https://doi.org/10.1109/TVLSI.2013.2275037},
doi = {10.1109/TVLSI.2013.2275037},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz14b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz14c,
author = {Irith Pomeranz},
title = {Low-Power Diagnostic Test Sets for Transition Faults Based on Functional
Broadside Tests},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {22},
number = {11},
pages = {2427--2431},
year = {2014},
url = {https://doi.org/10.1109/TVLSI.2013.2290768},
doi = {10.1109/TVLSI.2013.2290768},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz14c.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/Pomeranz14,
author = {Irith Pomeranz},
editor = {Gerhard P. Fettweis and
Wolfgang Nebel},
title = {Test and non-test cubes for diagnostic test generation based on merging
of test cubes},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2014, Dresden, Germany, March 24-28, 2014},
pages = {1--4},
publisher = {European Design and Automation Association},
year = {2014},
url = {https://doi.org/10.7873/DATE.2014.143},
doi = {10.7873/DATE.2014.143},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/Pomeranz14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/Pomeranz14a,
author = {Irith Pomeranz},
editor = {Gerhard P. Fettweis and
Wolfgang Nebel},
title = {Substituting transition faults with path delay faults as a basic delay
fault model},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2014, Dresden, Germany, March 24-28, 2014},
pages = {1--6},
publisher = {European Design and Automation Association},
year = {2014},
url = {https://doi.org/10.7873/DATE.2014.241},
doi = {10.7873/DATE.2014.241},
timestamp = {Tue, 23 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/Pomeranz14a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ets/Pomeranz14,
author = {Irith Pomeranz},
editor = {Giorgio Di Natale},
title = {A distance-based test cube merging procedure for compatible and incompatible
test cubes},
booktitle = {19th {IEEE} European Test Symposium, {ETS} 2014, Paderborn, Germany,
May 26-30, 2014},
pages = {1--2},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ETS.2014.6847824},
doi = {10.1109/ETS.2014.6847824},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/ets/Pomeranz14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/YaoPVA14,
author = {Bo Yao and
Irith Pomeranz and
Srikanth Venkataraman and
M. Enamul Amyeen},
editor = {Joseph R. Cavallaro and
Tong Zhang and
Alex K. Jones and
Hai (Helen) Li},
title = {Built-in generation of functional broadside tests considering primary
input constraints},
booktitle = {Great Lakes Symposium on {VLSI} 2014, {GLSVLSI} '14, Houston, TX,
{USA} - May 21 - 23, 2014},
pages = {237--238},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2591513.2591560},
doi = {10.1145/2591513.2591560},
timestamp = {Tue, 16 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/YaoPVA14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/Pomeranz14,
author = {Irith Pomeranz},
title = {{FDPIC:} Generation of Functional Test Sequences Based on Fault-Dependent
Primary Input Cubes},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2014, Tampa,
FL, USA, July 9-11, 2014},
pages = {308--313},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/ISVLSI.2014.23},
doi = {10.1109/ISVLSI.2014.23},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/Pomeranz14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/Pomeranz14a,
author = {Irith Pomeranz},
title = {{OBO:} An Output-by-Output Scoring Algorithm for Fault Diagnosis},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2014, Tampa,
FL, USA, July 9-11, 2014},
pages = {314--319},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/ISVLSI.2014.22},
doi = {10.1109/ISVLSI.2014.22},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/Pomeranz14a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/KapurP14,
author = {Rohit Kapur and
Irith Pomeranz},
title = {Innovative practices session 10C: Advances in {DFT} and compression},
booktitle = {32nd {IEEE} {VLSI} Test Symposium, {VTS} 2014, Napa, CA, USA, April
13-17, 2014},
pages = {1},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/VTS.2014.6818795},
doi = {10.1109/VTS.2014.6818795},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/KapurP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/Pomeranz14,
author = {Irith Pomeranz},
title = {Fault simulation with test switching for static test compaction},
booktitle = {32nd {IEEE} {VLSI} Test Symposium, {VTS} 2014, Napa, CA, USA, April
13-17, 2014},
pages = {1--6},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/VTS.2014.6818738},
doi = {10.1109/VTS.2014.6818738},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/Pomeranz14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/Pomeranz14a,
author = {Irith Pomeranz},
title = {On the use of multi-cycle tests for storage of two-cycle broadside
tests},
booktitle = {32nd {IEEE} {VLSI} Test Symposium, {VTS} 2014, Napa, CA, USA, April
13-17, 2014},
pages = {1--6},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/VTS.2014.6818796},
doi = {10.1109/VTS.2014.6818796},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/Pomeranz14a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/Pomeranz13,
author = {Irith Pomeranz},
title = {Static test compaction for mixed broadside and skewed-load transition
fault test sets},
journal = {{IET} Comput. Digit. Tech.},
volume = {7},
number = {1},
pages = {21--28},
year = {2013},
url = {https://doi.org/10.1049/iet-cdt.2012.0081},
doi = {10.1049/IET-CDT.2012.0081},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/Pomeranz13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/Pomeranz13a,
author = {Irith Pomeranz},
title = {On multi-cycle test cubes},
journal = {{IET} Comput. Digit. Tech.},
volume = {7},
number = {4},
pages = {182--189},
year = {2013},
url = {https://doi.org/10.1049/iet-cdt.2012.0140},
doi = {10.1049/IET-CDT.2012.0140},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/Pomeranz13a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijccbs/Pomeranz13,
author = {Irith Pomeranz},
title = {Low-power test sets under test-related primary input constraints},
journal = {Int. J. Crit. Comput. Based Syst.},
volume = {4},
number = {3},
pages = {265--279},
year = {2013},
url = {https://doi.org/10.1504/IJCCBS.2013.058396},
doi = {10.1504/IJCCBS.2013.058396},
timestamp = {Thu, 10 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijccbs/Pomeranz13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jolpe/Pomeranz13,
author = {Irith Pomeranz},
title = {Diagnostic Test Sets with Increased Switching Activity for Transition
Faults},
journal = {J. Low Power Electron.},
volume = {9},
number = {1},
pages = {133--140},
year = {2013},
url = {https://doi.org/10.1166/jolpe.2013.1248},
doi = {10.1166/JOLPE.2013.1248},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jolpe/Pomeranz13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/Pomeranz13,
author = {Irith Pomeranz},
title = {An Adjacent Switching Activity Metric under Functional Broadside Tests},
journal = {{IEEE} Trans. Computers},
volume = {62},
number = {2},
pages = {404--410},
year = {2013},
url = {https://doi.org/10.1109/TC.2011.224},
doi = {10.1109/TC.2011.224},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/Pomeranz13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/Pomeranz13a,
author = {Irith Pomeranz},
title = {Signal-Transition Patterns of Functional Broadside Tests},
journal = {{IEEE} Trans. Computers},
volume = {62},
number = {12},
pages = {2544--2549},
year = {2013},
url = {https://doi.org/10.1109/TC.2012.141},
doi = {10.1109/TC.2012.141},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/Pomeranz13a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz13,
author = {Irith Pomeranz},
title = {Generation of Functional Broadside Tests for Logic Blocks With Constrained
Primary Input Sequences},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {32},
number = {3},
pages = {442--452},
year = {2013},
url = {https://doi.org/10.1109/TCAD.2012.2227258},
doi = {10.1109/TCAD.2012.2227258},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz13a,
author = {Irith Pomeranz},
title = {Functional Broadside Tests With Incompletely Specified Scan-In States},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {32},
number = {9},
pages = {1445--1449},
year = {2013},
url = {https://doi.org/10.1109/TCAD.2013.2261121},
doi = {10.1109/TCAD.2013.2261121},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz13a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz13b,
author = {Irith Pomeranz},
title = {Non-Test Cubes for Test Generation Targeting Hard-to-Detect Faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {32},
number = {12},
pages = {1957--1965},
year = {2013},
url = {https://doi.org/10.1109/TCAD.2013.2275431},
doi = {10.1109/TCAD.2013.2275431},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz13b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/Pomeranz13,
author = {Irith Pomeranz},
title = {Built-in generation of multicycle functional broadside tests with
observation points},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {19},
number = {1},
pages = {8:1--8:17},
year = {2013},
url = {https://doi.org/10.1145/2534396},
doi = {10.1145/2534396},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/Pomeranz13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz13,
author = {Irith Pomeranz},
title = {Built-In Generation of Functional Broadside Tests Using a Fixed Hardware
Structure},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {1},
pages = {124--132},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2011.2179682},
doi = {10.1109/TVLSI.2011.2179682},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz13a,
author = {Irith Pomeranz},
title = {Computing Two-Pattern Test Cubes for Transition Path Delay Faults},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {3},
pages = {475--485},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2188727},
doi = {10.1109/TVLSI.2012.2188727},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz13a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz13b,
author = {Irith Pomeranz},
title = {Broadside and Skewed-Load Tests Under Primary Input Constraints},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {4},
pages = {776--780},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2192300},
doi = {10.1109/TVLSI.2012.2192300},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz13b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz13c,
author = {Irith Pomeranz},
title = {Reduced Power Transition Fault Test Sets for Circuits With Independent
Scan Chain Modes},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {7},
pages = {1354--1359},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2207137},
doi = {10.1109/TVLSI.2012.2207137},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz13c.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz13d,
author = {Irith Pomeranz},
title = {Transition Fault Simulation Considering Broadside Tests as Partially-Functional
Broadside Tests},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {7},
pages = {1359--1363},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2206835},
doi = {10.1109/TVLSI.2012.2206835},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz13d.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz13e,
author = {Irith Pomeranz},
title = {On Test Compaction of Broadside and Skewed-Load Test Cubes},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {9},
pages = {1705--1714},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2217360},
doi = {10.1109/TVLSI.2012.2217360},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz13e.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz13f,
author = {Irith Pomeranz},
title = {Functional Broadside Templates for Low-Power Test Generation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {12},
pages = {2321--2325},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2228510},
doi = {10.1109/TVLSI.2012.2228510},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz13f.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/Pomeranz13,
author = {Irith Pomeranz},
editor = {Enrico Macii},
title = {On candidate fault sets for fault diagnosis and dominance graphs of
equivalence classes},
booktitle = {Design, Automation and Test in Europe, {DATE} 13, Grenoble, France,
March 18-22, 2013},
pages = {1083--1088},
publisher = {{EDA} Consortium San Jose, CA, {USA} / {ACM} {DL}},
year = {2013},
url = {https://doi.org/10.7873/DATE.2013.228},
doi = {10.7873/DATE.2013.228},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/Pomeranz13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/Pomeranz13,
author = {Irith Pomeranz},
title = {Classes of difficult-to-diagnose transition fault clusters},
booktitle = {2013 {IEEE} International Symposium on Defect and Fault Tolerance
in {VLSI} and Nanotechnology Systems, {DFTS} 2013, New York City,
NY, USA, October 2-4, 2013},
pages = {1--6},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/DFT.2013.6653574},
doi = {10.1109/DFT.2013.6653574},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dft/Pomeranz13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ets/Pomeranz13,
author = {Irith Pomeranz},
title = {Generation of compact multi-cycle diagnostic test sets},
booktitle = {18th {IEEE} European Test Symposium, {ETS} 2013, Avignon, France,
May 27-30, 2013},
pages = {1},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/ETS.2013.6569382},
doi = {10.1109/ETS.2013.6569382},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ets/Pomeranz13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/YaoSP13,
author = {Bo Yao and
Arani Sinha and
Irith Pomeranz},
title = {Path selection based on static timing analysis considering input necessary
assignments},
booktitle = {31st {IEEE} {VLSI} Test Symposium, {VTS} 2013, Berkeley, CA, USA,
April 29 - May 2, 2013},
pages = {1--6},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/VTS.2013.6548902},
doi = {10.1109/VTS.2013.6548902},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/YaoSP13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/Pomeranz12,
author = {Irith Pomeranz},
title = {Test vector chains for increased resolution and reduced storage of
diagnostic tests},
journal = {{IET} Comput. Digit. Tech.},
volume = {6},
number = {1},
pages = {12--18},
year = {2012},
url = {https://doi.org/10.1049/iet-cdt.2010.0173},
doi = {10.1049/IET-CDT.2010.0173},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/Pomeranz12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/Pomeranz12a,
author = {Irith Pomeranz},
title = {Undetectable transition faults under broadside tests with constant
primary input vectors},
journal = {{IET} Comput. Digit. Tech.},
volume = {6},
number = {2},
pages = {78--85},
year = {2012},
url = {https://doi.org/10.1049/iet-cdt.2011.0097},
doi = {10.1049/IET-CDT.2011.0097},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/Pomeranz12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/Pomeranz12b,
author = {Irith Pomeranz},
title = {Functional broadside tests for embedded logic blocks},
journal = {{IET} Comput. Digit. Tech.},
volume = {6},
number = {4},
pages = {223--231},
year = {2012},
url = {https://doi.org/10.1049/iet-cdt.2011.0163},
doi = {10.1049/IET-CDT.2011.0163},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/Pomeranz12b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/PomeranzR12,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Reset and partial-reset-based functional broadside tests},
journal = {{IET} Comput. Digit. Tech.},
volume = {6},
number = {4},
pages = {232--239},
year = {2012},
url = {https://doi.org/10.1049/iet-cdt.2011.0131},
doi = {10.1049/IET-CDT.2011.0131},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/PomeranzR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/Pomeranz12,
author = {Irith Pomeranz},
title = {On the Computation of Common Test Data for Broadside and Skewed-Load
Tests},
journal = {{IEEE} Trans. Computers},
volume = {61},
number = {4},
pages = {578--583},
year = {2012},
url = {https://doi.org/10.1109/TC.2011.39},
doi = {10.1109/TC.2011.39},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/Pomeranz12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/Pomeranz12a,
author = {Irith Pomeranz},
title = {Concatenation of Functional Test Subsequences for Improved Fault Coverage
and Reduced Test Length},
journal = {{IEEE} Trans. Computers},
volume = {61},
number = {6},
pages = {899--904},
year = {2012},
url = {https://doi.org/10.1109/TC.2011.107},
doi = {10.1109/TC.2011.107},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/Pomeranz12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/Pomeranz12b,
author = {Irith Pomeranz},
title = {Fast Identification of Undetectable Transition Faults under Functional
Broadside Tests},
journal = {{IEEE} Trans. Computers},
volume = {61},
number = {6},
pages = {905--910},
year = {2012},
url = {https://doi.org/10.1109/TC.2011.111},
doi = {10.1109/TC.2011.111},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/Pomeranz12b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/Pomeranz12c,
author = {Irith Pomeranz},
title = {On the Switching Activity and Static Test Compaction of Multicycle
Scan-Based Tests},
journal = {{IEEE} Trans. Computers},
volume = {61},
number = {8},
pages = {1179--1188},
year = {2012},
url = {https://doi.org/10.1109/TC.2011.184},
doi = {10.1109/TC.2011.184},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/Pomeranz12c.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz12,
author = {Irith Pomeranz},
title = {Multipattern Scan-Based Test Sets With Small Numbers of Primary Input
Sequences},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {2},
pages = {322--326},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2170070},
doi = {10.1109/TCAD.2011.2170070},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz12a,
author = {Irith Pomeranz},
title = {Multicycle Tests With Constant Primary Input Vectors for Increased
Fault Coverage},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {9},
pages = {1428--1438},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2193583},
doi = {10.1109/TCAD.2012.2193583},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz12b,
author = {Irith Pomeranz},
title = {A Metric for Identifying Detectable Path Delay Faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {11},
pages = {1734--1742},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2201482},
doi = {10.1109/TCAD.2012.2201482},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz12b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PomeranzR12,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Resolution of Diagnosis Based on Transition Faults},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {1},
pages = {172--176},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2010.2091975},
doi = {10.1109/TVLSI.2010.2091975},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PomeranzR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz12,
author = {Irith Pomeranz},
title = {Gradual Diagnostic Test Generation and Observation Point Insertion
Based on the Structural Distance Between Indistinguished Fault Pairs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {6},
pages = {1026--1035},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2138729},
doi = {10.1109/TVLSI.2011.2138729},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz12a,
author = {Irith Pomeranz},
title = {Multi-Pattern {\textdollar}n{\textdollar}-Detection Stuck-At Test
Sets for Delay Defect Coverage},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {6},
pages = {1156--1160},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2144627},
doi = {10.1109/TVLSI.2011.2144627},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz12b,
author = {Irith Pomeranz},
title = {Generation of Mixed Test Sets for Transition Faults},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {10},
pages = {1895--1899},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2161786},
doi = {10.1109/TVLSI.2011.2161786},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz12b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz12c,
author = {Irith Pomeranz},
title = {Non-Uniform Coverage by n -Detection Test Sets},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {11},
pages = {2138--2142},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2168432},
doi = {10.1109/TVLSI.2011.2168432},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz12c.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/Pomeranz12,
author = {Irith Pomeranz},
title = {Generation and compaction of mixed broadside and skewed-load n-detection
test sets for transition faults},
booktitle = {2012 {IEEE} International Symposium on Defect and Fault Tolerance
in {VLSI} and Nanotechnology Systems, {DFT} 2012, Austin, TX, USA,
October 3-5, 2012},
pages = {37--42},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/DFT.2012.6378196},
doi = {10.1109/DFT.2012.6378196},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dft/Pomeranz12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/Pomeranz12a,
author = {Irith Pomeranz},
title = {Built-in generation of multi-cycle broadside tests},
booktitle = {2012 {IEEE} International Symposium on Defect and Fault Tolerance
in {VLSI} and Nanotechnology Systems, {DFT} 2012, Austin, TX, USA,
October 3-5, 2012},
pages = {146--151},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/DFT.2012.6378215},
doi = {10.1109/DFT.2012.6378215},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dft/Pomeranz12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/Pomeranz12b,
author = {Irith Pomeranz},
title = {Maintaining proximity to functional operation conditions under enhanced-scan
tests based on functional broadside tests},
booktitle = {2012 {IEEE} International Symposium on Defect and Fault Tolerance
in {VLSI} and Nanotechnology Systems, {DFT} 2012, Austin, TX, USA,
October 3-5, 2012},
pages = {239--244},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/DFT.2012.6378230},
doi = {10.1109/DFT.2012.6378230},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dft/Pomeranz12b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ets/Pomeranz12,
author = {Irith Pomeranz},
title = {On the detection of path delay faults by functional broadside tests},
booktitle = {17th {IEEE} European Test Symposium, {ETS} 2012, Annecy, France, May
28 - June 1 2012},
pages = {1--6},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/ETS.2012.6233015},
doi = {10.1109/ETS.2012.6233015},
timestamp = {Tue, 28 Apr 2020 11:43:43 +0200},
biburl = {https://dblp.org/rec/conf/ets/Pomeranz12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/0004R0P12,
author = {Amit Kumar and
Sudhakar M. Reddy and
Bernd Becker and
Irith Pomeranz},
title = {Performance aware partitioning for 3D-SOCs},
booktitle = {International SoC Design Conference, {ISOCC} 2012, Jeju Island, South
Korea, November 4-7, 2012},
pages = {163--166},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISOCC.2012.6407065},
doi = {10.1109/ISOCC.2012.6407065},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isocc/0004R0P12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/KumarRPB12,
author = {Amit Kumar and
Sudhakar M. Reddy and
Irith Pomeranz and
Bernd Becker},
editor = {Keith A. Bowman and
Kamesh V. Gadepally and
Pallab Chatterjee and
Mark M. Budnik and
Lalitha Immaneni},
title = {{TSV} and {DFT} cost aware circuit partitioning for 3D-SOCs},
booktitle = {Thirteenth International Symposium on Quality Electronic Design, {ISQED}
2012, Santa Clara, CA, USA, March 19-21, 2012},
pages = {21--26},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISQED.2012.6187469},
doi = {10.1109/ISQED.2012.6187469},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/KumarRPB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/Pomeranz12,
author = {Irith Pomeranz},
title = {Static test compaction for transition faults under the hazard-based
detection conditions},
booktitle = {30th {IEEE} {VLSI} Test Symposium, {VTS} 2012, Maui, Hawaii, USA,
23-26 April 2012},
pages = {176--181},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/VTS.2012.6231099},
doi = {10.1109/VTS.2012.6231099},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/vts/Pomeranz12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/PomeranzR11,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Primary input cones based on test sequences in synchronous sequential
circuits},
journal = {{IET} Comput. Digit. Tech.},
volume = {5},
number = {1},
pages = {16--24},
year = {2011},
url = {https://doi.org/10.1049/iet-cdt.2009.0087},
doi = {10.1049/IET-CDT.2009.0087},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/PomeranzR11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/PomeranzR11a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Two-dimensional partially functional broadside tests},
journal = {{IET} Comput. Digit. Tech.},
volume = {5},
number = {4},
pages = {247--253},
year = {2011},
url = {https://doi.org/10.1049/iet-cdt.2009.0022},
doi = {10.1049/IET-CDT.2009.0022},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/PomeranzR11a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/PomeranzR11b,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Sizes of test sets for path delay faults using strong and weak non-robust
tests},
journal = {{IET} Comput. Digit. Tech.},
volume = {5},
number = {5},
pages = {405--414},
year = {2011},
url = {https://doi.org/10.1049/iet-cdt.2010.0049},
doi = {10.1049/IET-CDT.2010.0049},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/PomeranzR11b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/PomeranzR11c,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Ranking of input cubes based on their lingering synchronisation effects
and their use in random sequential test generation},
journal = {{IET} Comput. Digit. Tech.},
volume = {5},
number = {5},
pages = {415--423},
year = {2011},
url = {https://doi.org/10.1049/iet-cdt.2010.0014},
doi = {10.1049/IET-CDT.2010.0014},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/PomeranzR11c.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jolpe/PomeranzR11,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Transparent-Segmented-Scan without the Routing Overhead of Segmented-Scan},
journal = {J. Low Power Electron.},
volume = {7},
number = {2},
pages = {245--253},
year = {2011},
url = {https://doi.org/10.1166/jolpe.2011.1132},
doi = {10.1166/JOLPE.2011.1132},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jolpe/PomeranzR11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz11,
author = {Irith Pomeranz},
title = {Generation of Multi-Cycle Broadside Tests},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {8},
pages = {1253--1257},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2138470},
doi = {10.1109/TCAD.2011.2138470},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz11a,
author = {Irith Pomeranz},
title = {Scan Shift Power of Functional Broadside Tests},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {9},
pages = {1416--1420},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2149890},
doi = {10.1109/TCAD.2011.2149890},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz11a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz11b,
author = {Irith Pomeranz},
title = {Subsets of Primary Input Vectors in Sequential Test Generation for
Single Stuck-at Faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {10},
pages = {1579--1583},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2157158},
doi = {10.1109/TCAD.2011.2157158},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz11b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/PomeranzR11,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Reducing the switching activity of test sequences under transparent-scan},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {2},
pages = {17:1--17:21},
year = {2011},
url = {https://doi.org/10.1145/1929943.1929949},
doi = {10.1145/1929943.1929949},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/PomeranzR11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PomeranzR11,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Fixed-State Tests for Delay Faults in Scan Designs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {19},
number = {1},
pages = {142--146},
year = {2011},
url = {https://doi.org/10.1109/TVLSI.2009.2030811},
doi = {10.1109/TVLSI.2009.2030811},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PomeranzR11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PomeranzR11a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Input Necessary Assignments for Testing of Path Delay Faults in Standard-Scan
Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {19},
number = {2},
pages = {333--337},
year = {2011},
url = {https://doi.org/10.1109/TVLSI.2009.2031865},
doi = {10.1109/TVLSI.2009.2031865},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PomeranzR11a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PomeranzR11b,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On Functional Broadside Tests With Functional Propagation Conditions},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {19},
number = {6},
pages = {1094--1098},
year = {2011},
url = {https://doi.org/10.1109/TVLSI.2010.2043695},
doi = {10.1109/TVLSI.2010.2043695},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PomeranzR11b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PomeranzR11c,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Broadside and Functional Broadside Tests for Partial-Scan Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {19},
number = {6},
pages = {1104--1108},
year = {2011},
url = {https://doi.org/10.1109/TVLSI.2010.2044049},
doi = {10.1109/TVLSI.2010.2044049},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PomeranzR11c.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PomeranzR11d,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Static Test Data Volume Reduction Using Complementation or Modulo-
{M} Addition},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {19},
number = {6},
pages = {1108--1112},
year = {2011},
url = {https://doi.org/10.1109/TVLSI.2010.2044819},
doi = {10.1109/TVLSI.2010.2044819},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PomeranzR11d.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PomeranzR11e,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Reducing the Storage Requirements of a Test Sequence by Using One
or Two Background Vectors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {19},
number = {10},
pages = {1755--1764},
year = {2011},
url = {https://doi.org/10.1109/TVLSI.2010.2055588},
doi = {10.1109/TVLSI.2010.2055588},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PomeranzR11e.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PomeranzR11f,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Test Strength: {A} Quality Metric for Transition Fault Tests in Full-Scan
Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {19},
number = {10},
pages = {1907--1911},
year = {2011},
url = {https://doi.org/10.1109/TVLSI.2010.2057459},
doi = {10.1109/TVLSI.2010.2057459},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PomeranzR11f.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/HowardRPB11,
author = {J. M. Howard and
Sudhakar M. Reddy and
Irith Pomeranz and
Bernd Becker},
title = {Fault diagnosis aware {ATE} assisted test response compaction},
booktitle = {Proceedings of the 16th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2011, Yokohama, Japan, January 25-27, 2011},
pages = {812--817},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ASPDAC.2011.5722302},
doi = {10.1109/ASPDAC.2011.5722302},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/HowardRPB11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/Pomeranz11,
author = {Irith Pomeranz},
editor = {Leon Stok and
Nikil D. Dutt and
Soha Hassoun},
title = {Diagnosis of transition fault clusters},
booktitle = {Proceedings of the 48th Design Automation Conference, {DAC} 2011,
San Diego, California, USA, June 5-10, 2011},
pages = {429--434},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/2024724.2024824},
doi = {10.1145/2024724.2024824},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/Pomeranz11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/Pomeranz11,
author = {Irith Pomeranz},
title = {Built-in generation of functional broadside tests},
booktitle = {Design, Automation and Test in Europe, {DATE} 2011, Grenoble, France,
March 14-18, 2011},
pages = {1297--1302},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/DATE.2011.5763208},
doi = {10.1109/DATE.2011.5763208},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/Pomeranz11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/KumarRPB11,
author = {Amit Kumar and
Sudhakar M. Reddy and
Irith Pomeranz and
Bernd Becker},
title = {Hyper-graph based partitioning to reduce {DFT} cost for pre-bond 3D-IC
testing},
booktitle = {Design, Automation and Test in Europe, {DATE} 2011, Grenoble, France,
March 14-18, 2011},
pages = {1424--1429},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/DATE.2011.5763230},
doi = {10.1109/DATE.2011.5763230},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/KumarRPB11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ddecs/FanRP11,
author = {Xiaoxin Fan and
Sudhakar M. Reddy and
Irith Pomeranz},
editor = {Rolf Kraemer and
Adam Pawlak and
Andreas Steininger and
Mario Sch{\"{o}}lzel and
Jaan Raik and
Heinrich Theodor Vierhaus},
title = {Max-Fill: {A} method to generate high quality delay tests},
booktitle = {14th {IEEE} International Symposium on Design and Diagnostics of Electronic
Circuits {\&} Systems, {DDECS} 2011, Cottbus, Germany, April 13-15,
2011},
pages = {375--380},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/DDECS.2011.5783114},
doi = {10.1109/DDECS.2011.5783114},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ddecs/FanRP11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ets/Pomeranz11,
author = {Irith Pomeranz},
title = {On Transition Fault Diagnosis Using Multicycle At-Speed Broadside
Tests},
booktitle = {16th European Test Symposium, {ETS} 2011, Trondheim, Norway, May 23-27,
2011},
pages = {189--194},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ETS.2011.14},
doi = {10.1109/ETS.2011.14},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ets/Pomeranz11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/prdc/Pomeranz11,
author = {Irith Pomeranz},
editor = {Leon Alkalai and
Timothy Tsai and
Tomohiro Yoneda},
title = {Augmenting Functional Broadside Tests for Transition Fault Coverage
with Bounded Switching Activity},
booktitle = {17th {IEEE} Pacific Rim International Symposium on Dependable Computing,
{PRDC} 2011, Pasadena, CA, USA, December 12-14, 2011},
pages = {38--44},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/PRDC.2011.14},
doi = {10.1109/PRDC.2011.14},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/prdc/Pomeranz11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/prdc/Pomeranz11a,
author = {Irith Pomeranz},
editor = {Leon Alkalai and
Timothy Tsai and
Tomohiro Yoneda},
title = {Generation of Mixed Broadside and Skewed-Load Diagnostic Test Sets
for Transition Faults},
booktitle = {17th {IEEE} Pacific Rim International Symposium on Dependable Computing,
{PRDC} 2011, Pasadena, CA, USA, December 12-14, 2011},
pages = {45--52},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/PRDC.2011.15},
doi = {10.1109/PRDC.2011.15},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/prdc/Pomeranz11a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/Pomeranz11,
author = {Irith Pomeranz},
title = {Static test compaction for delay fault test sets consisting of broadside
and skewed-load tests},
booktitle = {29th {IEEE} {VLSI} Test Symposium, {VTS} 2011, May 1-5, 2011, Dana
Point, California, {USA}},
pages = {84--89},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/VTS.2011.5783760},
doi = {10.1109/VTS.2011.5783760},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/vts/Pomeranz11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/Pomeranz11a,
author = {Irith Pomeranz},
title = {On clustering of undetectable transition faults in standard-scan circuits},
booktitle = {29th {IEEE} {VLSI} Test Symposium, {VTS} 2011, May 1-5, 2011, Dana
Point, California, {USA}},
pages = {128--133},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/VTS.2011.5783772},
doi = {10.1109/VTS.2011.5783772},
timestamp = {Thu, 25 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vts/Pomeranz11a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/PomeranzR10,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Diagnosis of path delay faults based on low-coverage tests},
journal = {{IET} Comput. Digit. Tech.},
volume = {4},
number = {2},
pages = {89--103},
year = {2010},
url = {https://doi.org/10.1049/iet-cdt.2008.0154},
doi = {10.1049/IET-CDT.2008.0154},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/PomeranzR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/PomeranzR10a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Static test compaction for diagnostic test sets of full-scan circuits},
journal = {{IET} Comput. Digit. Tech.},
volume = {4},
number = {5},
pages = {365--373},
year = {2010},
url = {https://doi.org/10.1049/iet-cdt.2009.0110},
doi = {10.1049/IET-CDT.2009.0110},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/PomeranzR10a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jolpe/PomeranzR10,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Test Sequences with Reduced and Increased Switching Activity},
journal = {J. Low Power Electron.},
volume = {6},
number = {2},
pages = {350--358},
year = {2010},
url = {https://doi.org/10.1166/jolpe.2010.1077},
doi = {10.1166/JOLPE.2010.1077},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jolpe/PomeranzR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/PomeranzR10,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Equivalence, Dominance, and Similarity Relations between Fault Pairs
and a Fault Pair Collapsing Process for Fault Diagnosis},
journal = {{IEEE} Trans. Computers},
volume = {59},
number = {2},
pages = {150--158},
year = {2010},
url = {https://doi.org/10.1109/TC.2009.112},
doi = {10.1109/TC.2009.112},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/PomeranzR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR10,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {{TOV:} Sequential Test Generation by Ordering of Test Vectors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {3},
pages = {454--465},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2041985},
doi = {10.1109/TCAD.2010.2041985},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR10a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On Test Generation With Test Vector Improvement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {3},
pages = {502--506},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2041853},
doi = {10.1109/TCAD.2010.2041853},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR10a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR10b,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On Clustering of Undetectable Single Stuck-At Faults and Test Quality
in Full-Scan Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {7},
pages = {1135--1140},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2046448},
doi = {10.1109/TCAD.2010.2046448},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR10b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR10c,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Hazard-Based Detection Conditions for Improved Transition Path Delay
Fault Coverage},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {9},
pages = {1449--1453},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2049462},
doi = {10.1109/TCAD.2010.2049462},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR10c.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR10d,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On Undetectable Faults and Fault Diagnosis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {11},
pages = {1832--1837},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2053476},
doi = {10.1109/TCAD.2010.2053476},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR10d.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PomeranzR10,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Hazard-Based Detection Conditions for Improved Transition Fault Coverage
of Scan-Based Tests},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {18},
number = {2},
pages = {333--337},
year = {2010},
url = {https://doi.org/10.1109/TVLSI.2008.2010216},
doi = {10.1109/TVLSI.2008.2010216},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PomeranzR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PomeranzR10a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Path Selection for Transition Path Delay Faults},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {18},
number = {3},
pages = {401--409},
year = {2010},
url = {https://doi.org/10.1109/TVLSI.2008.2011913},
doi = {10.1109/TVLSI.2008.2011913},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PomeranzR10a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PomeranzR10b,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Robust Fault Models Where Undetectable Faults Imply Logic Redundancy},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {18},
number = {8},
pages = {1230--1234},
year = {2010},
url = {https://doi.org/10.1109/TVLSI.2009.2020592},
doi = {10.1109/TVLSI.2009.2020592},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PomeranzR10b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PomeranzR10c,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Switching Activity as a Test Compaction Heuristic for Transition Faults},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {18},
number = {9},
pages = {1357--1361},
year = {2010},
url = {https://doi.org/10.1109/TVLSI.2009.2022474},
doi = {10.1109/TVLSI.2009.2022474},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PomeranzR10c.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PomeranzR10d,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Selection of a Fault Model for Fault Diagnosis Based on Unique Responses},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {18},
number = {11},
pages = {1533--1543},
year = {2010},
url = {https://doi.org/10.1109/TVLSI.2009.2025503},
doi = {10.1109/TVLSI.2009.2025503},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PomeranzR10d.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/PomeranzR10,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Functional and partially-functional skewed-load tests},
booktitle = {Proceedings of the 15th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2010, Taipei, Taiwan, January 18-21, 2010},
pages = {505--510},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ASPDAC.2010.5419832},
doi = {10.1109/ASPDAC.2010.5419832},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/PomeranzR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/PomeranzR10,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On Bias in Transition Coverage of Test Sets for Path Delay Faults},
booktitle = {Proceedings of the 19th {IEEE} Asian Test Symposium, {ATS} 2010, 1-4
December 2010, Shanghai, China},
pages = {349--352},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/ATS.2010.66},
doi = {10.1109/ATS.2010.66},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/PomeranzR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PomeranzR10,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Giovanni De Micheli and
Bashir M. Al{-}Hashimi and
Wolfgang M{\"{u}}ller and
Enrico Macii},
title = {Reducing the storage requirements of a test sequence by using a background
vector},
booktitle = {Design, Automation and Test in Europe, {DATE} 2010, Dresden, Germany,
March 8-12, 2010},
pages = {1237--1242},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/DATE.2010.5456996},
doi = {10.1109/DATE.2010.5456996},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/PomeranzR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PomeranzR10a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Giovanni De Micheli and
Bashir M. Al{-}Hashimi and
Wolfgang M{\"{u}}ller and
Enrico Macii},
title = {On reset based functional broadside tests},
booktitle = {Design, Automation and Test in Europe, {DATE} 2010, Dresden, Germany,
March 8-12, 2010},
pages = {1438--1443},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/DATE.2010.5457038},
doi = {10.1109/DATE.2010.5457038},
timestamp = {Tue, 23 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/PomeranzR10a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/PomeranzR10,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Gradual Diagnostic Test Generation Based on the Structural Distance
between Indistinguished Fault Pairs},
booktitle = {25th {IEEE} International Symposium on Defect and Fault Tolerance
in {VLSI} Systems, {DFT} 2010, Kyoto, Japan, October 6-8, 2010},
pages = {349--357},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/DFT.2010.49},
doi = {10.1109/DFT.2010.49},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dft/PomeranzR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ets/PomeranzR10,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Input test data volume reduction based on test vector chains},
booktitle = {15th European Test Symposium, {ETS} 2010, Prague, Czech Republic,
May 24-28, 2010},
pages = {240},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/ETSYM.2010.5512753},
doi = {10.1109/ETSYM.2010.5512753},
timestamp = {Tue, 28 Apr 2020 11:43:44 +0200},
biburl = {https://dblp.org/rec/conf/ets/PomeranzR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/YaoPR10,
author = {Bo Yao and
Irith Pomeranz and
Sudhakar M. Reddy},
editor = {R. Iris Bahar and
Fabrizio Lombardi and
David Atienza and
Erik Brunvand},
title = {Deterministic broadside test generation for transition path delay
faults},
booktitle = {Proceedings of the 20th {ACM} Great Lakes Symposium on {VLSI} 2009,
Providence, Rhode Island, USA, May 16-18 2010},
pages = {135--138},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1785481.1785514},
doi = {10.1145/1785481.1785514},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/YaoPR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iolts/PomeranzR10,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Selecting state variables for improved on-line testability through
output response comparison of identical circuits},
booktitle = {16th {IEEE} International On-Line Testing Symposium {(IOLTS} 2010),
5-7 July, 2010, Corfu, Greece},
pages = {179--184},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/IOLTS.2010.5560213},
doi = {10.1109/IOLTS.2010.5560213},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iolts/PomeranzR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/Devta-PrasannaGRP10,
author = {Narendra Devta{-}Prasanna and
Arun Gunda and
Sudhakar M. Reddy and
Irith Pomeranz},
editor = {Ron Press and
Erik H. Volkerink},
title = {Multiple fault activation cycle tests for transistor stuck-open faults},
booktitle = {2011 {IEEE} International Test Conference, {ITC} 2010, Austin, TX,
USA, November 2-4, 2010},
pages = {821},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/TEST.2010.5699313},
doi = {10.1109/TEST.2010.5699313},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/Devta-PrasannaGRP10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/PomeranzR10,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Output-Dependent Diagnostic Test Generation},
booktitle = {{VLSI} Design 2010: 23rd International Conference on {VLSI} Design,
9th International Conference on Embedded Systems, Bangalore, India,
3-7 January 2010},
pages = {3--8},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/VLSI.Design.2010.13},
doi = {10.1109/VLSI.DESIGN.2010.13},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/PomeranzR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/PomeranzR10a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Identifying Tests for Logic Fault Models Involving Subsets of Lines
without Fault Enumeration},
booktitle = {{VLSI} Design 2010: 23rd International Conference on {VLSI} Design,
9th International Conference on Embedded Systems, Bangalore, India,
3-7 January 2010},
pages = {39--44},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/VLSI.Design.2010.16},
doi = {10.1109/VLSI.DESIGN.2010.16},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/PomeranzR10a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/PomeranzR10,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Forming multi-cycle tests for delay faults by concatenating broadside
tests},
booktitle = {28th {IEEE} {VLSI} Test Symposium, {VTS} 2010, April 19-22, 2010,
Santa Cruz, California, {USA}},
pages = {51--56},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/VTS.2010.5469616},
doi = {10.1109/VTS.2010.5469616},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/vts/PomeranzR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/KimPAV10,
author = {Dongok Kim and
Irith Pomeranz and
M. Enamul Amyeen and
Srikanth Venkataraman},
title = {Defect diagnosis based on {DFM} guidelines},
booktitle = {28th {IEEE} {VLSI} Test Symposium, {VTS} 2010, April 19-22, 2010,
Santa Cruz, California, {USA}},
pages = {206--211},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/VTS.2010.5469577},
doi = {10.1109/VTS.2010.5469577},
timestamp = {Tue, 16 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/KimPAV10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/PomeranzR10a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On multiple bridging faults},
booktitle = {28th {IEEE} {VLSI} Test Symposium, {VTS} 2010, April 19-22, 2010,
Santa Cruz, California, {USA}},
pages = {221--226},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/VTS.2010.5469573},
doi = {10.1109/VTS.2010.5469573},
timestamp = {Thu, 25 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vts/PomeranzR10a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/PomeranzR09,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Definition and generation of partially-functional broadside tests},
journal = {{IET} Comput. Digit. Tech.},
volume = {3},
number = {1},
pages = {1--13},
year = {2009},
url = {https://doi.org/10.1049/iet-cdt:20070144},
doi = {10.1049/IET-CDT:20070144},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/PomeranzR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/PomeranzR09a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Same/different fault dictionary: an extended pass/fail fault dictionary
with improved diagnostic resolution},
journal = {{IET} Comput. Digit. Tech.},
volume = {3},
number = {1},
pages = {85--93},
year = {2009},
url = {https://doi.org/10.1049/iet-cdt:20080017},
doi = {10.1049/IET-CDT:20080017},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/PomeranzR09a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/PomeranzR09b,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Test vector chains for increasing the fault coverage and numbers of
detections},
journal = {{IET} Comput. Digit. Tech.},
volume = {3},
number = {2},
pages = {222--233},
year = {2009},
url = {https://doi.org/10.1049/iet-cdt:20080056},
doi = {10.1049/IET-CDT:20080056},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/PomeranzR09b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/PomeranzR09c,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Test compaction methods for transition faults under transparent-scan},
journal = {{IET} Comput. Digit. Tech.},
volume = {3},
number = {4},
pages = {315--328},
year = {2009},
url = {https://doi.org/10.1049/iet-cdt.2008.0115},
doi = {10.1049/IET-CDT.2008.0115},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/PomeranzR09c.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR09,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Functional Broadside Tests Under an Expanded Definition of Functional
Operation Conditions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {1},
pages = {121--129},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2008.2009152},
doi = {10.1109/TCAD.2008.2009152},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR09a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Double-Single Stuck-at Faults: {A} Delay Fault Model for Synchronous
Sequential Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {3},
pages = {426--432},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2013281},
doi = {10.1109/TCAD.2009.2013281},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR09a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR09b,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Forward-Looking Reverse Order Fault Simulation for n -Detection Test
Sets},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {9},
pages = {1424--1428},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2023193},
doi = {10.1109/TCAD.2009.2023193},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR09b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tdsc/PomeranzR09,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Semiconcurrent Online Testing of Transition Faults through Output
Response Comparison of Identical Circuits},
journal = {{IEEE} Trans. Dependable Secur. Comput.},
volume = {6},
number = {3},
pages = {231--240},
year = {2009},
url = {https://doi.org/10.1109/TDSC.2008.34},
doi = {10.1109/TDSC.2008.34},
timestamp = {Thu, 09 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tdsc/PomeranzR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/PomeranzR09,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Using stuck-at tests to form scan-based tests for transition faults
in standard-scan circuits},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {15},
number = {1},
pages = {7:1--7:22},
year = {2009},
url = {https://doi.org/10.1145/1640457.1640464},
doi = {10.1145/1640457.1640464},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/PomeranzR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PomeranzR09,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Random Test Generation With Input Cube Avoidance},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {17},
number = {1},
pages = {45--54},
year = {2009},
url = {https://doi.org/10.1109/TVLSI.2008.2001943},
doi = {10.1109/TVLSI.2008.2001943},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PomeranzR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/PomeranzR09,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Kazutoshi Wakabayashi},
title = {Dynamic test compaction for a random test generation procedure with
input cube avoidance},
booktitle = {Proceedings of the 14th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2009, Yokohama, Japan, January 19-22, 2009},
pages = {672--677},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/ASPDAC.2009.4796557},
doi = {10.1109/ASPDAC.2009.4796557},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/PomeranzR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/YangCDRP09,
author = {Fan Yang and
Sreejit Chakravarty and
Narendra Devta{-}Prasanna and
Sudhakar M. Reddy and
Irith Pomeranz},
editor = {Kazutoshi Wakabayashi},
title = {Detectability of internal bridging faults in scan chains},
booktitle = {Proceedings of the 14th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2009, Yokohama, Japan, January 19-22, 2009},
pages = {678--683},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/ASPDAC.2009.4796558},
doi = {10.1109/ASPDAC.2009.4796558},
timestamp = {Thu, 21 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/YangCDRP09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/PomeranzR09,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Fault Diagnosis under Transparent-Scan},
booktitle = {Proceedings of the Eighteentgh Asian Test Symposium, {ATS} 2009, 23-26
November 2009, Taichung, Taiwan},
pages = {29--34},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/ATS.2009.12},
doi = {10.1109/ATS.2009.12},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/PomeranzR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/ChenRRP09,
author = {Gang Chen and
Janusz Rajski and
Sudhakar M. Reddy and
Irith Pomeranz},
title = {N-distinguishing Tests for Enhanced Defect Diagnosis},
booktitle = {Proceedings of the Eighteentgh Asian Test Symposium, {ATS} 2009, 23-26
November 2009, Taichung, Taiwan},
pages = {183--186},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/ATS.2009.47},
doi = {10.1109/ATS.2009.47},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/ChenRRP09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PomeranzR09,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Luca Benini and
Giovanni De Micheli and
Bashir M. Al{-}Hashimi and
Wolfgang M{\"{u}}ller},
title = {Selection of a fault model for fault diagnosis based on unique responses},
booktitle = {Design, Automation and Test in Europe, {DATE} 2009, Nice, France,
April 20-24, 2009},
pages = {994--999},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/DATE.2009.5090809},
doi = {10.1109/DATE.2009.5090809},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/PomeranzR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/RemersaroRRP09,
author = {Santiago Remersaro and
Janusz Rajski and
Sudhakar M. Reddy and
Irith Pomeranz},
editor = {Luca Benini and
Giovanni De Micheli and
Bashir M. Al{-}Hashimi and
Wolfgang M{\"{u}}ller},
title = {A scalable method for the generation of small test sets},
booktitle = {Design, Automation and Test in Europe, {DATE} 2009, Nice, France,
April 20-24, 2009},
pages = {1136--1141},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/DATE.2009.5090834},
doi = {10.1109/DATE.2009.5090834},
timestamp = {Tue, 23 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/RemersaroRRP09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/PomeranzR09,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Dimitris Gizopoulos and
Susumu Horiguchi and
Spyros Tragoudas and
Mohammad Tehranipoor},
title = {On-chip Generation of the Second Primary Input Vectors of Broadside
Tests},
booktitle = {24th {IEEE} International Symposium on Defect and Fault Tolerance
in {VLSI} Systems, {DFT} 2009, Chicago, Illinois, USA, October 7-9,
2009},
pages = {38--46},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/DFT.2009.12},
doi = {10.1109/DFT.2009.12},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dft/PomeranzR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/PomeranzR09a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Dimitris Gizopoulos and
Susumu Horiguchi and
Spyros Tragoudas and
Mohammad Tehranipoor},
title = {Hazard-Based Detection Conditions for Improved Transition Fault Coverage
of Functional Test Sequences},
booktitle = {24th {IEEE} International Symposium on Defect and Fault Tolerance
in {VLSI} Systems, {DFT} 2009, Chicago, Illinois, USA, October 7-9,
2009},
pages = {358--366},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/DFT.2009.11},
doi = {10.1109/DFT.2009.11},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dft/PomeranzR09a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/YangCDRP09,
author = {Fan Yang and
Sreejit Chakravarty and
Narendra Devta{-}Prasanna and
Sudhakar M. Reddy and
Irith Pomeranz},
editor = {Dimitris Gizopoulos and
Susumu Horiguchi and
Spyros Tragoudas and
Mohammad Tehranipoor},
title = {Improving the Detectability of Resistive Open Faults in Scan Cells},
booktitle = {24th {IEEE} International Symposium on Defect and Fault Tolerance
in {VLSI} Systems, {DFT} 2009, Chicago, Illinois, USA, October 7-9,
2009},
pages = {383--391},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/DFT.2009.30},
doi = {10.1109/DFT.2009.30},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dft/YangCDRP09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ets/PomeranzR09,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Input Cubes with Lingering Synchronization Effects and their Use in
Random Sequential Test Generation},
booktitle = {14th {IEEE} European Test Symposium, {ETS} 2009, Sevilla, Spain, May
25-29, 2009},
pages = {87--92},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/ETS.2009.19},
doi = {10.1109/ETS.2009.19},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ets/PomeranzR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/PomeranzR09,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Fabrizio Lombardi and
Sanjukta Bhanja and
Yehia Massoud and
R. Iris Bahar},
title = {Partitioned n-detection test generation},
booktitle = {Proceedings of the 19th {ACM} Great Lakes Symposium on {VLSI} 2009,
Boston Area, MA, USA, May 10-12 2009},
pages = {93--98},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1531542.1531566},
doi = {10.1145/1531542.1531566},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/PomeranzR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/PomeranzR09a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Fabrizio Lombardi and
Sanjukta Bhanja and
Yehia Massoud and
R. Iris Bahar},
title = {Definition and application of approximate necessary assignments},
booktitle = {Proceedings of the 19th {ACM} Great Lakes Symposium on {VLSI} 2009,
Boston Area, MA, USA, May 10-12 2009},
pages = {105--108},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1531542.1531569},
doi = {10.1145/1531542.1531569},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/PomeranzR09a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/PomeranzR09b,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Fabrizio Lombardi and
Sanjukta Bhanja and
Yehia Massoud and
R. Iris Bahar},
title = {State persistence: a property for guiding test generation},
booktitle = {Proceedings of the 19th {ACM} Great Lakes Symposium on {VLSI} 2009,
Boston Area, MA, USA, May 10-12 2009},
pages = {523--528},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1531542.1531660},
doi = {10.1145/1531542.1531660},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/PomeranzR09b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/PomeranzR09,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {The Effect of Filling the Unspecified Values of a Test Set on the
Test Set Quality},
booktitle = {{VLSI} Design 2009: Improving Productivity through Higher Abstraction,
The 22nd International Conference on {VLSI} Design, New Delhi, India,
5-9 January 2009},
pages = {215--220},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/VLSI.Design.2009.11},
doi = {10.1109/VLSI.DESIGN.2009.11},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/PomeranzR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jolpe/PomeranzR08,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Functional Broadside Tests with Minimum and Maximum Switching Activity},
journal = {J. Low Power Electron.},
volume = {4},
number = {3},
pages = {429--437},
year = {2008},
url = {https://doi.org/10.1166/jolpe.2008.196},
doi = {10.1166/JOLPE.2008.196},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jolpe/PomeranzR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR08,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Unspecified Transition Faults: {A} Transition Fault Model for At-Speed
Fault Simulation and Test Generation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {1},
pages = {137--146},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.907000},
doi = {10.1109/TCAD.2007.907000},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR08a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Primary Input Vectors to Avoid in Random Test Sequences for Synchronous
Sequential Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {1},
pages = {193--197},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.907229},
doi = {10.1109/TCAD.2007.907229},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR08a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR08b,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Scan-Based Delay Test Types and Their Effect on Power Dissipation
During Test},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {2},
pages = {398--403},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2007.907231},
doi = {10.1109/TCAD.2007.907231},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR08b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeePR08,
author = {Hangkyu Lee and
Irith Pomeranz and
Sudhakar M. Reddy},
title = {On Complete Functional Broadside Tests for Transition Faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {3},
pages = {583--587},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.915531},
doi = {10.1109/TCAD.2008.915531},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeePR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR08c,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On the Saturation of n-Detection Test Generation by Different Definitions
With Increased n},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {5},
pages = {946--957},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.917577},
doi = {10.1109/TCAD.2008.917577},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR08c.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PomeranzR08,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Transition Path Delay Faults: {A} New Path Delay Fault Model for Small
and Large Delay Defects},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {16},
number = {1},
pages = {98--107},
year = {2008},
url = {https://doi.org/10.1109/TVLSI.2007.909796},
doi = {10.1109/TVLSI.2007.909796},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PomeranzR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PomeranzR08a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Improving the Transition Fault Coverage of Functional Broadside Tests
by Observation Point Insertion},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {16},
number = {7},
pages = {931--936},
year = {2008},
url = {https://doi.org/10.1109/TVLSI.2008.2000453},
doi = {10.1109/TVLSI.2008.2000453},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PomeranzR08a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/PomeranzR08,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Chong{-}Min Kyung and
Kiyoung Choi and
Soonhoi Ha},
title = {Circuit lines for guiding the generation of random test sequences
for synchronous sequential circuits},
booktitle = {Proceedings of the 13th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2008, Seoul, Korea, January 21-24, 2008},
pages = {641--646},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/ASPDAC.2008.4484030},
doi = {10.1109/ASPDAC.2008.4484030},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/PomeranzR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/PomeranzR08a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Chong{-}Min Kyung and
Kiyoung Choi and
Soonhoi Ha},
title = {Test vector chains for increased targeted and untargeted fault coverage},
booktitle = {Proceedings of the 13th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2008, Seoul, Korea, January 21-24, 2008},
pages = {663--666},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/ASPDAC.2008.4484034},
doi = {10.1109/ASPDAC.2008.4484034},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/PomeranzR08a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/KimPAV08,
author = {Dongok Kim and
Irith Pomeranz and
M. Enamul Amyeen and
Srikanth Venkataraman},
title = {Prioritizing the Application of {DFM} Guidelines Based on the Detectability
of Systematic Defects},
booktitle = {17th {IEEE} Asian Test Symposium, {ATS} 2008, Sapporo, Japan, November
24-27, 2008},
pages = {217--220},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/ATS.2008.69},
doi = {10.1109/ATS.2008.69},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/KimPAV08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/ReddyPL08,
author = {Sudhakar M. Reddy and
Irith Pomeranz and
Chen Liu},
editor = {Limor Fix},
title = {On tests to detect via opens in digital {CMOS} circuits},
booktitle = {Proceedings of the 45th Design Automation Conference, {DAC} 2008,
Anaheim, CA, USA, June 8-13, 2008},
pages = {840--845},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1391469.1391682},
doi = {10.1145/1391469.1391682},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/ReddyPL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PomeranzR08,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Donatella Sciuto},
title = {A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy},
booktitle = {Design, Automation and Test in Europe, {DATE} 2008, Munich, Germany,
March 10-14, 2008},
pages = {1166--1171},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1109/DATE.2008.4484836},
doi = {10.1109/DATE.2008.4484836},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/PomeranzR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PomeranzR08a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Donatella Sciuto},
title = {A Same/Different Fault Dictionary: An Extended Pass/Fail Fault Dictionary
with Improved Diagnostic Resolution},
booktitle = {Design, Automation and Test in Europe, {DATE} 2008, Munich, Germany,
March 10-14, 2008},
pages = {1474--1479},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1109/DATE.2008.4484882},
doi = {10.1109/DATE.2008.4484882},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/PomeranzR08a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/PolianRPTB08,
author = {Ilia Polian and
Sudhakar M. Reddy and
Irith Pomeranz and
Xun Tang and
Bernd Becker},
editor = {Cristiana Bolchini and
Yong{-}Bin Kim and
Dimitris Gizopoulos and
Mohammad Tehranipoor},
title = {On Reducing Circuit Malfunctions Caused by Soft Errors},
booktitle = {23rd {IEEE} International Symposium on Defect and Fault-Tolerance
in {VLSI} Systems {(DFT} 2008), 1-3 October 2008, Boston, MA, {USA}},
pages = {245--253},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/DFT.2008.20},
doi = {10.1109/DFT.2008.20},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dft/PolianRPTB08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/RemersaroRRRP08,
author = {Santiago Remersaro and
Janusz Rajski and
Thomas Rinderknecht and
Sudhakar M. Reddy and
Irith Pomeranz},
editor = {Cristiana Bolchini and
Yong{-}Bin Kim and
Dimitris Gizopoulos and
Mohammad Tehranipoor},
title = {{ATPG} Heuristics Dependant Observation Point Insertion for Enhanced
Compaction and Data Volume Reduction},
booktitle = {23rd {IEEE} International Symposium on Defect and Fault-Tolerance
in {VLSI} Systems {(DFT} 2008), 1-3 October 2008, Boston, MA, {USA}},
pages = {385--393},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/DFT.2008.39},
doi = {10.1109/DFT.2008.39},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dft/RemersaroRRRP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/YangCDRP08,
author = {Fan Yang and
Sreejit Chakravarty and
Narendra Devta{-}Prasanna and
Sudhakar M. Reddy and
Irith Pomeranz},
editor = {Cristiana Bolchini and
Yong{-}Bin Kim and
Dimitris Gizopoulos and
Mohammad Tehranipoor},
title = {Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of
Scan Cells},
booktitle = {23rd {IEEE} International Symposium on Defect and Fault-Tolerance
in {VLSI} Systems {(DFT} 2008), 1-3 October 2008, Boston, MA, {USA}},
pages = {394--402},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/DFT.2008.11},
doi = {10.1109/DFT.2008.11},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dft/YangCDRP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ets/PomeranzR08,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Safe Fault Collapsing Based on Dominance Relations},
booktitle = {13th European Test Symposium, {ETS} 2008, Verbania, Italy, May 25-29,
2008},
pages = {7--12},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/ETS.2008.11},
doi = {10.1109/ETS.2008.11},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ets/PomeranzR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iolts/YangCDRP08,
author = {Fan Yang and
Sreejit Chakravarty and
Narendra Devta{-}Prasanna and
Sudhakar M. Reddy and
Irith Pomeranz},
title = {An Enhanced Logic {BIST} Architecture for Online Testing},
booktitle = {14th {IEEE} International On-Line Testing Symposium {(IOLTS} 2008),
7-9 July 2008, Rhodes, Greece},
pages = {10--15},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/IOLTS.2008.48},
doi = {10.1109/IOLTS.2008.48},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iolts/YangCDRP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/YangCDRP08,
author = {Fan Yang and
Sreejit Chakravarty and
Narendra Devta{-}Prasanna and
Sudhakar M. Reddy and
Irith Pomeranz},
editor = {Douglas Young and
Nur A. Touba},
title = {Detection of Internal Stuck-open Faults in Scan Chains},
booktitle = {2008 {IEEE} International Test Conference, {ITC} 2008, Santa Clara,
California, USA, October 26-31, 2008},
pages = {1--10},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/TEST.2008.4700577},
doi = {10.1109/TEST.2008.4700577},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/YangCDRP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/PomeranzRK08,
author = {Irith Pomeranz and
Sudhakar M. Reddy and
Sandip Kundu},
title = {On Common-Mode Skewed-Load and Broadside Tests},
booktitle = {21st International Conference on {VLSI} Design {(VLSI} Design 2008),
4-8 January 2008, Hyderabad, India},
pages = {151--156},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/VLSI.2008.16},
doi = {10.1109/VLSI.2008.16},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/PomeranzRK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/PomeranzR08,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Design-for-Testability for Improved Path Delay Fault Coverage of Critical
Paths},
booktitle = {21st International Conference on {VLSI} Design {(VLSI} Design 2008),
4-8 January 2008, Hyderabad, India},
pages = {175--180},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/VLSI.2008.22},
doi = {10.1109/VLSI.2008.22},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/PomeranzR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/PomeranzR08a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Design-for-Testability for Synchronous Sequential Circuits that Maintains
Functional Switching Activity},
booktitle = {21st International Conference on {VLSI} Design {(VLSI} Design 2008),
4-8 January 2008, Hyderabad, India},
pages = {181--186},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/VLSI.2008.17},
doi = {10.1109/VLSI.2008.17},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/PomeranzR08a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/YangCDRP08,
author = {Fan Yang and
Sreejit Chakravarty and
Narendra Devta{-}Prasanna and
Sudhakar M. Reddy and
Irith Pomeranz},
title = {On the Detectability of Scan Chain Internal Faults - An Industrial
Case Study},
booktitle = {26th {IEEE} {VLSI} Test Symposium {(VTS} 2008), April 27 - May 1,
2008, San Diego, California, {USA}},
pages = {79--84},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/VTS.2008.13},
doi = {10.1109/VTS.2008.13},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/YangCDRP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/PomeranzR08,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Synthesis for Broadside Testability of Transition Faults},
booktitle = {26th {IEEE} {VLSI} Test Symposium {(VTS} 2008), April 27 - May 1,
2008, San Diego, California, {USA}},
pages = {221--226},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/VTS.2008.10},
doi = {10.1109/VTS.2008.10},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/PomeranzR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/PomeranzR08a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Expanded Definition of Functional Operation Conditions and its Effects
on the Computation of Functional Broadside Tests},
booktitle = {26th {IEEE} {VLSI} Test Symposium {(VTS} 2008), April 27 - May 1,
2008, San Diego, California, {USA}},
pages = {317--322},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/VTS.2008.11},
doi = {10.1109/VTS.2008.11},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/PomeranzR08a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/RemersaroLRPR07,
author = {Santiago Remersaro and
Xijiang Lin and
Sudhakar M. Reddy and
Irith Pomeranz and
Janusz Rajski},
title = {Scan-Based Tests with Low Switching Activity},
journal = {{IEEE} Des. Test Comput.},
volume = {24},
number = {3},
pages = {268--275},
year = {2007},
url = {https://doi.org/10.1109/MDT.2007.80},
doi = {10.1109/MDT.2007.80},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/RemersaroLRPR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/ZhangRPRA07,
author = {Zhuo Zhang and
Sudhakar M. Reddy and
Irith Pomeranz and
Janusz Rajski and
Bashir M. Al{-}Hashimi},
title = {Enhancing delay fault coverage through low-power segmented scan},
journal = {{IET} Comput. Digit. Tech.},
volume = {1},
number = {3},
pages = {220--229},
year = {2007},
url = {https://doi.org/10.1049/iet-cdt:20060135},
doi = {10.1049/IET-CDT:20060135},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/ZhangRPRA07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/PomeranzR07,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Worst-case and average-case analysis of n-detection test sets and
test generation strategies},
journal = {{IET} Comput. Digit. Tech.},
volume = {1},
number = {4},
pages = {353--363},
year = {2007},
url = {https://doi.org/10.1049/iet-cdt:20060120},
doi = {10.1049/IET-CDT:20060120},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/PomeranzR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/PomeranzR07a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Effectiveness of scan-based delay fault tests in diagnosis of transition
faults},
journal = {{IET} Comput. Digit. Tech.},
volume = {1},
number = {5},
pages = {537--545},
year = {2007},
url = {https://doi.org/10.1049/iet-cdt:20070029},
doi = {10.1049/IET-CDT:20070029},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/PomeranzR07a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz07,
author = {Irith Pomeranz},
title = {Invariant States and Redundant Logic in Synchronous Sequential Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {6},
pages = {1171--1175},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.885832},
doi = {10.1109/TCAD.2006.885832},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR07,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Generation of Broadside Transition-Fault Test Sets That Detect Four-Way
Bridging Faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {7},
pages = {1311--1319},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.891370},
doi = {10.1109/TCAD.2007.891370},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzRV07,
author = {Irith Pomeranz and
Sudhakar M. Reddy and
Srikanth Venkataraman},
title = {z-Diagnosis: {A} Framework for Diagnostic Fault Simulation and Test
Generation Utilizing Subsets of Outputs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {9},
pages = {1700--1712},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.895758},
doi = {10.1109/TCAD.2007.895758},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzRV07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/PomeranzR07,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Forming N-detection test sets without test generation},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {12},
number = {2},
pages = {18},
year = {2007},
url = {https://doi.org/10.1145/1230800.1230810},
doi = {10.1145/1230800.1230810},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/PomeranzR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ZhangRP07,
author = {Zhuo Zhang and
Sudhakar M. Reddy and
Irith Pomeranz},
title = {Warning: Launch off Shift Tests for Delay Faults May Contribute to
Test Escapes},
booktitle = {Proceedings of the 12th Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2007, Yokohama, Japan, January 23-26, 2007},
pages = {817--822},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ASPDAC.2007.358090},
doi = {10.1109/ASPDAC.2007.358090},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/ZhangRP07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/PomeranzPP07,
author = {Irith Pomeranz and
Praveen Parvathala and
Srinivas Patil},
title = {Estimating the Fault Coverage of Functional Test Sequences Without
Fault Simulation},
booktitle = {16th Asian Test Symposium, {ATS} 2007, Beijing, China, October 8-11,
2007},
pages = {25--32},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/ATS.2007.18},
doi = {10.1109/ATS.2007.18},
timestamp = {Wed, 09 Nov 2022 21:30:34 +0100},
biburl = {https://dblp.org/rec/conf/ats/PomeranzPP07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/PomeranzR07,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Diagnostic Test Generation Targeting Equivalence Classes},
booktitle = {16th Asian Test Symposium, {ATS} 2007, Beijing, China, October 8-11,
2007},
pages = {301--306},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/ATS.2007.15},
doi = {10.1109/ATS.2007.15},
timestamp = {Wed, 09 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/PomeranzR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/PomeranzR07a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Enhanced Broadside Testing for Improved Transition Fault Coverage},
booktitle = {16th Asian Test Symposium, {ATS} 2007, Beijing, China, October 8-11,
2007},
pages = {479--484},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/ATS.2007.85},
doi = {10.1109/ATS.2007.85},
timestamp = {Wed, 09 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/PomeranzR07a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PomeranzR07,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Rudy Lauwereins and
Jan Madsen},
title = {On test generation by input cube avoidance},
booktitle = {2007 Design, Automation and Test in Europe Conference and Exposition,
{DATE} 2007, Nice, France, April 16-20, 2007},
pages = {522--527},
publisher = {{EDA} Consortium, San Jose, CA, {USA}},
year = {2007},
url = {https://doi.org/10.1109/DATE.2007.364646},
doi = {10.1109/DATE.2007.364646},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/PomeranzR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/PomeranzR07,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Cristiana Bolchini and
Yong{-}Bin Kim and
Adelio Salsano and
Nur A. Touba},
title = {A-Diagnosis: {A} Complement to Z-Diagnosis},
booktitle = {22nd {IEEE} International Symposium on Defect and Fault-Tolerance
in {VLSI} Systems {(DFT} 2007), 26-28 September 2007, Rome, Italy},
pages = {235--242},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/DFT.2007.9},
doi = {10.1109/DFT.2007.9},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dft/PomeranzR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/PomeranzR07a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Cristiana Bolchini and
Yong{-}Bin Kim and
Adelio Salsano and
Nur A. Touba},
title = {Semi-Concurrent On-Line Testing of Transition Faults Through Output
Response Comparison of Identical Circuits},
booktitle = {22nd {IEEE} International Symposium on Defect and Fault-Tolerance
in {VLSI} Systems {(DFT} 2007), 26-28 September 2007, Rome, Italy},
pages = {457--455},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/DFT.2007.10},
doi = {10.1109/DFT.2007.10},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dft/PomeranzR07a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ets/PomeranzR07,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Diagnostic Test Generation Based on Subsets of Faults},
booktitle = {12th European Test Symposium, {ETS} 2007, Freiburg, Germany, May 20,
2007},
pages = {151--158},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ETS.2007.17},
doi = {10.1109/ETS.2007.17},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ets/PomeranzR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/KimAVPBL07,
author = {Dongok Kim and
M. Enamul Amyeen and
Srikanth Venkataraman and
Irith Pomeranz and
Swagato Basumallick and
Berni Landau},
editor = {Jill Sibert and
Janusz Rajski},
title = {Testing for systematic defects based on {DFM} guidelines},
booktitle = {2007 {IEEE} International Test Conference, {ITC} 2007, Santa Clara,
California, USA, October 21-26, 2007},
pages = {1--10},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/TEST.2007.4437603},
doi = {10.1109/TEST.2007.4437603},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/KimAVPBL07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/PomeranzR07,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Jill Sibert and
Janusz Rajski},
title = {On the saturation of n-detection test sets with increased n},
booktitle = {2007 {IEEE} International Test Conference, {ITC} 2007, Santa Clara,
California, USA, October 21-26, 2007},
pages = {1--10},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/TEST.2007.4437647},
doi = {10.1109/TEST.2007.4437647},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/PomeranzR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/PomeranzR07,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Equivalence and Dominance Relations Between Fault Pairs and Their
Use in Fault Pair Collapsing for Fault Diagnosis},
booktitle = {20th International Conference on {VLSI} Design {(VLSI} Design 2007),
Sixth International Conference on Embedded Systems {(ICES} 2007),
6-10 January 2007, Bangalore, India},
pages = {498--503},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/VLSID.2007.78},
doi = {10.1109/VLSID.2007.78},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/PomeranzR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/RemersaroLRPR07,
author = {Santiago Remersaro and
Xijiang Lin and
Sudhakar M. Reddy and
Irith Pomeranz and
Janusz Rajski},
title = {Low Shift and Capture Power Scan Tests},
booktitle = {20th International Conference on {VLSI} Design {(VLSI} Design 2007),
Sixth International Conference on Embedded Systems {(ICES} 2007),
6-10 January 2007, Bangalore, India},
pages = {793--798},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/VLSID.2007.101},
doi = {10.1109/VLSID.2007.101},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/RemersaroLRPR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/PomeranzR07a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Functional Broadside Tests with Different Levels of Reachability},
booktitle = {20th International Conference on {VLSI} Design {(VLSI} Design 2007),
Sixth International Conference on Embedded Systems {(ICES} 2007),
6-10 January 2007, Bangalore, India},
pages = {799--804},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/VLSID.2007.87},
doi = {10.1109/VLSID.2007.87},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/PomeranzR07a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/PomeranzR07,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Autoscan-Invert: An Improved Scan Design without External Scan Inputs
or Outputs},
booktitle = {25th {IEEE} {VLSI} Test Symposium {(VTS} 2007), 6-10 May 2007, Berkeley,
California, {USA}},
pages = {416--421},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/VTS.2007.19},
doi = {10.1109/VTS.2007.19},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/PomeranzR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-0710-4637,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan
Circuits},
journal = {CoRR},
volume = {abs/0710.4637},
year = {2007},
url = {http://arxiv.org/abs/0710.4637},
eprinttype = {arXiv},
eprint = {0710.4637},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-0710-4637.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-0710-4735,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Worst-Case and Average-Case Analysis of n-Detection Test Sets},
journal = {CoRR},
volume = {abs/0710.4735},
year = {2007},
url = {http://arxiv.org/abs/0710.4735},
eprinttype = {arXiv},
eprint = {0710.4735},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-0710-4735.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/HigamiKPKT06,
author = {Yoshinobu Higami and
Seiji Kajihara and
Irith Pomeranz and
Shin{-}ya Kobayashi and
Yuzo Takamatsu},
title = {On Finding Don't Cares in Test Sequences for Sequential Circuits},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {89-D},
number = {11},
pages = {2748--2755},
year = {2006},
url = {https://doi.org/10.1093/ietisy/e89-d.11.2748},
doi = {10.1093/IETISY/E89-D.11.2748},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/HigamiKPKT06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/PomeranzR06,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On Generating Tests that Avoid the Detection of Redundant Faults in
Synchronous Sequential Circuits with Full Scan},
journal = {{IEEE} Trans. Computers},
volume = {55},
number = {4},
pages = {491--495},
year = {2006},
url = {https://doi.org/10.1109/TC.2006.57},
doi = {10.1109/TC.2006.57},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/PomeranzR06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR06,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Scan-BIST based on transition probabilities for circuits with single
and multiple scan chains},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {3},
pages = {591--596},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.854634},
doi = {10.1109/TCAD.2005.854634},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR06a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Transparent {DFT:} a design for testability and test generation approach
for synchronous sequential circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {6},
pages = {1170--1175},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855947},
doi = {10.1109/TCAD.2005.855947},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR06a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR06b,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Generation of Functional Broadside Tests for Transition Faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {10},
pages = {2207--2218},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.860959},
doi = {10.1109/TCAD.2005.860959},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR06b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR06c,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Using Dummy Bridging Faults to Define Reduced Sets of Target Faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {10},
pages = {2219--2227},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.860951},
doi = {10.1109/TCAD.2005.860951},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR06c.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR06d,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Improved n-Detection Test Sequences Under Transparent Scan},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {11},
pages = {2492--2501},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2006.881334},
doi = {10.1109/TCAD.2006.881334},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR06d.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/PomeranzPP06,
author = {Irith Pomeranz and
Srinivas Patil and
Praveen Parvathala},
title = {A Functional Fault Model with Implicit Fault Effect Propagation Requirements},
booktitle = {15th Asian Test Symposium, {ATS} 2006, Fukuoka, Japan, November 20-23,
2006},
pages = {95--102},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ATS.2006.260999},
doi = {10.1109/ATS.2006.260999},
timestamp = {Mon, 07 Nov 2022 17:39:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/PomeranzPP06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/Pomeranz06,
author = {Irith Pomeranz},
title = {To Overtest Or Not To Overtest - More Questions Than Answers},
booktitle = {15th Asian Test Symposium, {ATS} 2006, Fukuoka, Japan, November 20-23,
2006},
pages = {125},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ATS.2006.261003},
doi = {10.1109/ATS.2006.261003},
timestamp = {Mon, 07 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/Pomeranz06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/PomeranzR06,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On the Replacement of Scan Chain Inputs by Primary Input Vectors},
booktitle = {15th Asian Test Symposium, {ATS} 2006, Fukuoka, Japan, November 20-23,
2006},
pages = {175--182},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ATS.2006.261017},
doi = {10.1109/ATS.2006.261017},
timestamp = {Mon, 07 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/PomeranzR06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/ChenRPR06,
author = {Gang Chen and
Sudhakar M. Reddy and
Irith Pomeranz and
Janusz Rajski},
editor = {Ellen Sentovich},
title = {A test pattern ordering algorithm for diagnosis with truncated fail
data},
booktitle = {Proceedings of the 43rd Design Automation Conference, {DAC} 2006,
San Francisco, CA, USA, July 24-28, 2006},
pages = {399--404},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1146909.1147015},
doi = {10.1145/1146909.1147015},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/ChenRPR06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PomeranzR06,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Georges G. E. Gielen},
title = {Generation of broadside transition fault test sets that detect four-way
bridging faults},
booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe,
{DATE} 2006, Munich, Germany, March 6-10, 2006},
pages = {907--912},
publisher = {European Design and Automation Association, Leuven, Belgium},
year = {2006},
url = {https://doi.org/10.1109/DATE.2006.243806},
doi = {10.1109/DATE.2006.243806},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/PomeranzR06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PomeranzR06a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Georges G. E. Gielen},
title = {Test compaction for transition faults under transparent-scan},
booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe,
{DATE} 2006, Munich, Germany, March 6-10, 2006},
pages = {1264--1269},
publisher = {European Design and Automation Association, Leuven, Belgium},
year = {2006},
url = {https://doi.org/10.1109/DATE.2006.244098},
doi = {10.1109/DATE.2006.244098},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/PomeranzR06a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/DevtaprasannaGKRP06,
author = {Narendra Devta{-}Prasanna and
Arun Gunda and
P. Krishnamurthy and
Sudhakar M. Reddy and
Irith Pomeranz},
title = {Test Generation for Open Defects in {CMOS} Circuits},
booktitle = {21th {IEEE} International Symposium on Defect and Fault-Tolerance
in {VLSI} Systems {(DFT} 2006), 4-6 October 2006, Arlington, Virginia,
{USA}},
pages = {41--49},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/DFT.2006.62},
doi = {10.1109/DFT.2006.62},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dft/DevtaprasannaGKRP06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/LeeNPP06,
author = {Hangkyu Lee and
Suriyaprakash Natarajan and
Srinivas Patil and
Irith Pomeranz},
title = {Selecting High-Quality Delay Tests for Manufacturing Test and Debug},
booktitle = {21th {IEEE} International Symposium on Defect and Fault-Tolerance
in {VLSI} Systems {(DFT} 2006), 4-6 October 2006, Arlington, Virginia,
{USA}},
pages = {59--70},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/DFT.2006.57},
doi = {10.1109/DFT.2006.57},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dft/LeeNPP06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/PomeranzR06,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Scan-Based Delay Fault Tests for Diagnosis of Transition Faults},
booktitle = {21th {IEEE} International Symposium on Defect and Fault-Tolerance
in {VLSI} Systems {(DFT} 2006), 4-6 October 2006, Arlington, Virginia,
{USA}},
pages = {419--427},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/DFT.2006.56},
doi = {10.1109/DFT.2006.56},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dft/PomeranzR06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ets/ZhangRPRA06,
author = {Zhuo Zhang and
Sudhakar M. Reddy and
Irith Pomeranz and
Janusz Rajski and
Bashir M. Al{-}Hashimi},
title = {Enhancing Delay Fault Coverage through Low Power Segmented Scan},
booktitle = {11th European Test Symposium, {ETS} 2006, Southhampton, UK, May 21-24,
2006},
pages = {21--28},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/ETS.2006.18},
doi = {10.1109/ETS.2006.18},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ets/ZhangRPRA06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ets/PomeranzR06,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Fault Collapsing for Transition Faults Using Extended Transition Faults},
booktitle = {11th European Test Symposium, {ETS} 2006, Southhampton, UK, May 21-24,
2006},
pages = {173--178},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/ETS.2006.22},
doi = {10.1109/ETS.2006.22},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ets/PomeranzR06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ets/DevtaprasannaGKRP06,
author = {Narendra Devta{-}Prasanna and
Arun Gunda and
P. Krishnamurthy and
Sudhakar M. Reddy and
Irith Pomeranz},
title = {A Unified Method to Detect Transistor Stuck-Open Faults and Transition
Delay Faults},
booktitle = {11th European Test Symposium, {ETS} 2006, Southhampton, UK, May 21-24,
2006},
pages = {185--192},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/ETS.2006.8},
doi = {10.1109/ETS.2006.8},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ets/DevtaprasannaGKRP06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/PomeranzR06,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Soha Hassoun},
title = {A delay fault model for at-speed fault simulation and test generation},
booktitle = {2006 International Conference on Computer-Aided Design, {ICCAD} 2006,
San Jose, CA, USA, November 5-9, 2006},
pages = {89--95},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1233501.1233521},
doi = {10.1145/1233501.1233521},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/PomeranzR06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iolts/YuRP06,
author = {Chaowen Yu and
Sudhakar M. Reddy and
Irith Pomeranz},
title = {A Partitioning Technique for Identification of Error-Capturing Scan
Cells in Scan-BIST},
booktitle = {12th {IEEE} International On-Line Testing Symposium {(IOLTS} 2006),
10-12 July 2006, Como, Italy},
pages = {37--42},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/IOLTS.2006.9},
doi = {10.1109/IOLTS.2006.9},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iolts/YuRP06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/ParkCPPP06,
author = {Sungchul Park and
Li Chen and
Praveen Parvathala and
Srinivas Patil and
Irith Pomeranz},
editor = {Scott Davidson and
Anne Gattiker},
title = {A Functional Coverage Metric for Estimating the Gate-Level Fault Coverage
of Functional Tests},
booktitle = {2006 {IEEE} International Test Conference, {ITC} 2006, Santa Clara,
CA, USA, October 22-27, 2006},
pages = {1--10},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/TEST.2006.297674},
doi = {10.1109/TEST.2006.297674},
timestamp = {Tue, 12 Dec 2023 09:46:27 +0100},
biburl = {https://dblp.org/rec/conf/itc/ParkCPPP06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/PomeranzR06,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Scott Davidson and
Anne Gattiker},
title = {Fault Detection by Output Response Comparison of Identical Circuits
Using Half-Frequency Compatible Sequences},
booktitle = {2006 {IEEE} International Test Conference, {ITC} 2006, Santa Clara,
CA, USA, October 22-27, 2006},
pages = {1--10},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/TEST.2006.297658},
doi = {10.1109/TEST.2006.297658},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/itc/PomeranzR06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/RemersaroLZRPR06,
author = {Santiago Remersaro and
Xijiang Lin and
Zhuo Zhang and
Sudhakar M. Reddy and
Irith Pomeranz and
Janusz Rajski},
editor = {Scott Davidson and
Anne Gattiker},
title = {Preferred Fill: {A} Scalable Method to Reduce Capture Power for Scan
Based Designs},
booktitle = {2006 {IEEE} International Test Conference, {ITC} 2006, Santa Clara,
CA, USA, October 22-27, 2006},
pages = {1--10},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/TEST.2006.297694},
doi = {10.1109/TEST.2006.297694},
timestamp = {Wed, 25 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/RemersaroLZRPR06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/ChenRPR06,
author = {Gang Chen and
Sudhakar M. Reddy and
Irith Pomeranz and
Janusz Rajski},
title = {New Procedures to Identify Redundant Stuck-At Faults and Removal of
Redundant Logic},
booktitle = {19th International Conference on {VLSI} Design {(VLSI} Design 2006),
3-7 January 2006, Hyderabad, India},
pages = {419--424},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/VLSID.2006.120},
doi = {10.1109/VLSID.2006.120},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/ChenRPR06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/PomeranzR06,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {The Cut Delay Fault Model for Guiding the Generation of n-Detection
Test Sets for Transition Faults},
booktitle = {19th International Conference on {VLSI} Design {(VLSI} Design 2006),
3-7 January 2006, Hyderabad, India},
pages = {828--831},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/VLSID.2006.160},
doi = {10.1109/VLSID.2006.160},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/PomeranzR06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/LeePR06,
author = {Hangkyu Lee and
Irith Pomeranz and
Sudhakar M. Reddy},
title = {A Test Generation Procedure for Avoiding the Detection of Functionally
Redundant Transition Faults},
booktitle = {24th {IEEE} {VLSI} Test Symposium {(VTS} 2006), 30 April - 4 May 2006,
Berkeley, California, {USA}},
pages = {294--299},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/VTS.2006.13},
doi = {10.1109/VTS.2006.13},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/LeePR06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/ZhangRPLR06,
author = {Zhuo Zhang and
Sudhakar M. Reddy and
Irith Pomeranz and
Xijiang Lin and
Janusz Rajski},
title = {Scan Tests with Multiple Fault Activation Cycles for Delay Faults},
booktitle = {24th {IEEE} {VLSI} Test Symposium {(VTS} 2006), 30 April - 4 May 2006,
Berkeley, California, {USA}},
pages = {343--348},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/VTS.2006.91},
doi = {10.1109/VTS.2006.91},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/ZhangRPLR06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/SeshadriPVAR06,
author = {Bharath Seshadri and
Irith Pomeranz and
Srikanth Venkataraman and
M. Enamul Amyeen and
Sudhakar M. Reddy},
title = {Dominance Based Analysis for Large Volume Production Fail Diagnosis},
booktitle = {24th {IEEE} {VLSI} Test Symposium {(VTS} 2006), 30 April - 4 May 2006,
Berkeley, California, {USA}},
pages = {392--399},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/VTS.2006.29},
doi = {10.1109/VTS.2006.29},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/SeshadriPVAR06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:journals/entcs/PomeranzR07,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Roderick Bloem and
Marco Roveri and
Fabio Somenzi},
title = {On the Use of Functional Test Generation in Diagnostic Test Generation
for Synchronous Sequential Circuits},
booktitle = {Proceedings of the Workshop on Verification and Debugging, V{\&}D@FLoC
2006, Seattle, WA, USA, August 21, 2006},
series = {Electronic Notes in Theoretical Computer Science},
volume = {174},
number = {4},
pages = {83--93},
publisher = {Elsevier},
year = {2006},
url = {https://doi.org/10.1016/j.entcs.2006.12.031},
doi = {10.1016/J.ENTCS.2006.12.031},
timestamp = {Fri, 27 Jan 2023 12:15:31 +0100},
biburl = {https://dblp.org/rec/journals/entcs/PomeranzR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR05,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On masking of redundant faults in synchronous sequential circuits
with design-for-testability logic},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {24},
number = {2},
pages = {288--294},
year = {2005},
url = {https://doi.org/10.1109/TCAD.2004.840551},
doi = {10.1109/TCAD.2004.840551},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR05a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On fault equivalence, fault dominance, and incompletely specified
test sets},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {24},
number = {8},
pages = {1271--1274},
year = {2005},
url = {https://doi.org/10.1109/TCAD.2005.850822},
doi = {10.1109/TCAD.2005.850822},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR05a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChoPR05,
author = {Yonsang Cho and
Irith Pomeranz and
Sudhakar M. Reddy},
title = {On reducing test application time for scan circuits using limited
scan operations and transfer sequences},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {24},
number = {10},
pages = {1594--1605},
year = {2005},
url = {https://doi.org/10.1109/TCAD.2005.852285},
doi = {10.1109/TCAD.2005.852285},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChoPR05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tdsc/PomeranzR05,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Concurrent Online Testing of Identical Circuits Using Nonidentical
Input Vectors},
journal = {{IEEE} Trans. Dependable Secur. Comput.},
volume = {2},
number = {3},
pages = {190--200},
year = {2005},
url = {https://doi.org/10.1109/TDSC.2005.30},
doi = {10.1109/TDSC.2005.30},
timestamp = {Thu, 09 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tdsc/PomeranzR05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PomeranzR05,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Autoscan: a scan design without external scan inputs or outputs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {9},
pages = {1087--1095},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.857157},
doi = {10.1109/TVLSI.2005.857157},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PomeranzR05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/YuRP05,
author = {Chaowen Yu and
Sudhakar M. Reddy and
Irith Pomeranz},
title = {Circuit Independent Weighted Pseudo-Random {BIST} Pattern Generator},
booktitle = {14th Asian Test Symposium {(ATS} 2005), 18-21 December 2005, Calcutta,
India},
pages = {132--137},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ATS.2005.37},
doi = {10.1109/ATS.2005.37},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/YuRP05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/DevtaprasannaRGKP05,
author = {Narendra Devta{-}Prasanna and
Sudhakar M. Reddy and
Arun Gunda and
P. Krishnamurthy and
Irith Pomeranz},
title = {Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch
Transitions},
booktitle = {14th Asian Test Symposium {(ATS} 2005), 18-21 December 2005, Calcutta,
India},
pages = {202--207},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ATS.2005.68},
doi = {10.1109/ATS.2005.68},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/DevtaprasannaRGKP05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/Pomeranz05,
author = {Irith Pomeranz},
editor = {William H. Joyner Jr. and
Grant Martin and
Andrew B. Kahng},
title = {N-detection under transparent-scan},
booktitle = {Proceedings of the 42nd Design Automation Conference, {DAC} 2005,
San Diego, CA, USA, June 13-17, 2005},
pages = {129--134},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1065579.1065616},
doi = {10.1145/1065579.1065616},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/Pomeranz05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PomeranzR05,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Worst-Case and Average-Case Analysis of n-Detection Test Sets},
booktitle = {2005 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2005), 7-11 March 2005, Munich, Germany},
pages = {444--449},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/DATE.2005.330},
doi = {10.1109/DATE.2005.330},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/PomeranzR05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/TangCRWRP05,
author = {Huaxing Tang and
Gang Chen and
Sudhakar M. Reddy and
Chen Wang and
Janusz Rajski and
Irith Pomeranz},
title = {Defect Aware Test Patterns},
booktitle = {2005 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2005), 7-11 March 2005, Munich, Germany},
pages = {450--455},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/DATE.2005.110},
doi = {10.1109/DATE.2005.110},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/TangCRWRP05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PomeranzR05a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan
Circuits},
booktitle = {2005 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2005), 7-11 March 2005, Munich, Germany},
pages = {1008--1013},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/DATE.2005.306},
doi = {10.1109/DATE.2005.306},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/PomeranzR05a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/ZhangRP05,
author = {Zhuo Zhang and
Sudhakar M. Reddy and
Irith Pomeranz},
title = {On Generating Pseudo-Functional Delay Fault Tests for Scan Designs},
booktitle = {20th {IEEE} International Symposium on Defect and Fault-Tolerance
in {VLSI} Systems {(DFT} 2005), 3-5 October 2005, Monterey, CA, {USA}},
pages = {398--405},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/DFTVS.2005.49},
doi = {10.1109/DFTVS.2005.49},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dft/ZhangRP05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/PomeranzR05,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Recovery During Concurrent On-Line Testing of Identical Circuits},
booktitle = {20th {IEEE} International Symposium on Defect and Fault-Tolerance
in {VLSI} Systems {(DFT} 2005), 3-5 October 2005, Monterey, CA, {USA}},
pages = {475--483},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/DFTVS.2005.56},
doi = {10.1109/DFTVS.2005.56},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dft/PomeranzR05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ets/0011RPREB05,
author = {Gang Chen and
Sudhakar M. Reddy and
Irith Pomeranz and
Janusz Rajski and
Piet Engelke and
Bernd Becker},
title = {A unified fault model and test generation procedure for interconnect
opens and bridges},
booktitle = {10th European Test Symposium, {ETS} 2005, Tallinn, Estonia, May 22-25,
2005},
pages = {22--27},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ETS.2005.6},
doi = {10.1109/ETS.2005.6},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ets/0011RPREB05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ets/PomeranzR05,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Using dummy bridging faults to define a reduced set of target faults},
booktitle = {10th European Test Symposium, {ETS} 2005, Tallinn, Estonia, May 22-25,
2005},
pages = {42--47},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ETS.2005.45},
doi = {10.1109/ETS.2005.45},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ets/PomeranzR05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ets/SeshadriPRK05,
author = {Bharath Seshadri and
Irith Pomeranz and
Sudhakar M. Reddy and
Sandip Kundu},
title = {Path-oriented transition fault test generation considering operating
conditions},
booktitle = {10th European Test Symposium, {ETS} 2005, Tallinn, Estonia, May 22-25,
2005},
pages = {54--59},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ETS.2005.31},
doi = {10.1109/ETS.2005.31},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ets/SeshadriPRK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/DevtaprasannaGKRP05,
author = {Narendra Devta{-}Prasanna and
Arun Gunda and
P. Krishnamurthy and
Sudhakar M. Reddy and
Irith Pomeranz},
title = {A Novel Method of Improving Transition Delay Fault Coverage Using
Multiple Scan Enable Signals},
booktitle = {23rd International Conference on Computer Design {(ICCD} 2005), 2-5
October 2005, San Jose, CA, {USA}},
pages = {471--474},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ICCD.2005.13},
doi = {10.1109/ICCD.2005.13},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/DevtaprasannaGKRP05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/CaiRPA05,
author = {Yuan Cai and
Sudhakar M. Reddy and
Irith Pomeranz and
Bashir M. Al{-}Hashimi},
title = {Battery-aware dynamic voltage scaling in multiprocessor embedded system},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26
May 2005, Kobe, Japan},
pages = {616--619},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/ISCAS.2005.1464663},
doi = {10.1109/ISCAS.2005.1464663},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/CaiRPA05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/PomeranzR05,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Dynamic Test Compaction for Bridging Faults},
booktitle = {6th International Symposium on Quality of Electronic Design {(ISQED}
2005), 21-23 March 2005, San Jose, CA, {USA}},
pages = {250--255},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISQED.2005.48},
doi = {10.1109/ISQED.2005.48},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/PomeranzR05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/LiRP05,
author = {Wei Li and
Sudhakar M. Reddy and
Irith Pomeranz},
title = {On Reducing Peak Current and Power during Test},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {156--161},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.53},
doi = {10.1109/ISVLSI.2005.53},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/LiRP05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/PomeranzVR05,
author = {Irith Pomeranz and
Srikanth Venkataraman and
Sudhakar M. Reddy},
title = {Fault Diagnosis and Fault Model Aliasing},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {206--211},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.34},
doi = {10.1109/ISVLSI.2005.34},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/PomeranzVR05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/PomeranzR05,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Forming N-detection test sets from one-detection test sets without
test generation},
booktitle = {Proceedings 2005 {IEEE} International Test Conference, {ITC} 2005,
Austin, TX, USA, November 8-10, 2005},
pages = {9},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/TEST.2005.1584013},
doi = {10.1109/TEST.2005.1584013},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/PomeranzR05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/Devta-PrasannaGKRP05,
author = {Narendra Devta{-}Prasanna and
Arun Gunda and
P. Krishnamurthy and
Sudhakar M. Reddy and
Irith Pomeranz},
title = {Methods for improving transition delay fault coverage using broadside
tests},
booktitle = {Proceedings 2005 {IEEE} International Test Conference, {ITC} 2005,
Austin, TX, USA, November 8-10, 2005},
pages = {10},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/TEST.2005.1583983},
doi = {10.1109/TEST.2005.1583983},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/Devta-PrasannaGKRP05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/PomeranzR05,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Tuple Detection for Path Delay Faults: {A} Method for Improving Test
Set Quality},
booktitle = {18th International Conference on {VLSI} Design {(VLSI} Design 2005),
with the 4th International Conference on Embedded Systems Design,
3-7 January 2005, Kolkata, India},
pages = {41--46},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ICVD.2005.165},
doi = {10.1109/ICVD.2005.165},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/PomeranzR05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/TangWRRTP05,
author = {Huaxing Tang and
Chen Wang and
Janusz Rajski and
Sudhakar M. Reddy and
Jerzy Tyszer and
Irith Pomeranz},
title = {On Efficient X-Handling Using a Selective Compaction Scheme to Achieve
High Test Response Compaction Ratios},
booktitle = {18th International Conference on {VLSI} Design {(VLSI} Design 2005),
with the 4th International Conference on Embedded Systems Design,
3-7 January 2005, Kolkata, India},
pages = {59--64},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ICVD.2005.127},
doi = {10.1109/ICVD.2005.127},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/TangWRRTP05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/KajiharaTMPR04,
author = {Seiji Kajihara and
Kenjiro Taniguchi and
Kohei Miyase and
Irith Pomeranz and
Sudhakar M. Reddy},
title = {Don't Care Identification and Statistical Encoding for Test Data Compression},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {87-D},
number = {3},
pages = {544--550},
year = {2004},
url = {http://search.ieice.org/bin/summary.php?id=e87-d\_3\_544},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/KajiharaTMPR04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/PomeranzKR04,
author = {Irith Pomeranz and
Sandip Kundu and
Sudhakar M. Reddy},
title = {Masking of Unknown Output Values during Output Response Compression
byUsing Comparison Units},
journal = {{IEEE} Trans. Computers},
volume = {53},
number = {1},
pages = {83--88},
year = {2004},
url = {https://doi.org/10.1109/TC.2004.1255794},
doi = {10.1109/TC.2004.1255794},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/PomeranzKR04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/PomeranzR04,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On Maximizing the Fault Coverage for a Given Test Length Limit in
a Synchronous Sequential Circuit},
journal = {{IEEE} Trans. Computers},
volume = {53},
number = {9},
pages = {1121--1133},
year = {2004},
url = {https://doi.org/10.1109/TC.2004.63},
doi = {10.1109/TC.2004.63},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/PomeranzR04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/PomeranzR04a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {A Measure of Quality for n-Detection Test Sets},
journal = {{IEEE} Trans. Computers},
volume = {53},
number = {11},
pages = {1497--1503},
year = {2004},
url = {https://doi.org/10.1109/TC.2004.87},
doi = {10.1109/TC.2004.87},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/PomeranzR04a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/PomeranzR04b,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Static Test Compaction for Full-Scan Circuits Based on Combinational
Test Sets and Nonscan Input Sequences and a Lower Bound on the Number
of Tests},
journal = {{IEEE} Trans. Computers},
volume = {53},
number = {12},
pages = {1569--1581},
year = {2004},
url = {https://doi.org/10.1109/TC.2004.118},
doi = {10.1109/TC.2004.118},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/PomeranzR04b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz04,
author = {Irith Pomeranz},
title = {Constrained test generation for embedded synchronous sequential circuits
with serial-input access},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {23},
number = {1},
pages = {164--172},
year = {2004},
url = {https://doi.org/10.1109/TCAD.2003.819886},
doi = {10.1109/TCAD.2003.819886},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz04a,
author = {Irith Pomeranz},
title = {Reducing test-data volume using P-testable scan chains in circuits
with multiple scan chains},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {23},
number = {10},
pages = {1465--1478},
year = {2004},
url = {https://doi.org/10.1109/TCAD.2004.835131},
doi = {10.1109/TCAD.2004.835131},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz04a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR04,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Vector-restoration-based static compaction using random initial omission},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {23},
number = {11},
pages = {1587--1592},
year = {2004},
url = {https://doi.org/10.1109/TCAD.2004.836720},
doi = {10.1109/TCAD.2004.836720},
timestamp = {Tue, 16 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzRK04,
author = {Irith Pomeranz and
Sudhakar M. Reddy and
Sandip Kundu},
title = {On the characterization and efficient computation of hard-to-detect
bridging faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {23},
number = {12},
pages = {1640--1649},
year = {2004},
url = {https://doi.org/10.1109/TCAD.2004.837725},
doi = {10.1109/TCAD.2004.837725},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzRK04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PomeranzR04,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Improving the stuck-at fault coverage of functional test sequences
by using limited-scan operations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {12},
number = {7},
pages = {780--788},
year = {2004},
url = {https://doi.org/10.1109/TVLSI.2004.830910},
doi = {10.1109/TVLSI.2004.830910},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PomeranzR04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PomeranzZ04,
author = {Irith Pomeranz and
Yervant Zorian},
title = {Fault isolation for nonisolated blocks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {12},
number = {12},
pages = {1385--1388},
year = {2004},
url = {https://doi.org/10.1109/TVLSI.2004.837994},
doi = {10.1109/TVLSI.2004.837994},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PomeranzZ04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/PomeranzR04,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Properties of Maximally Dominating Faults},
booktitle = {13th Asian Test Symposium {(ATS} 2004), 15-17 November 2004, Kenting,
Taiwan},
pages = {106--111},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/ATS.2004.70},
doi = {10.1109/ATS.2004.70},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/PomeranzR04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/YuRP04,
author = {Chaowen Yu and
Sudhakar M. Reddy and
Irith Pomeranz},
title = {Weighted Pseudo-Random {BIST} for N-Detection of Single Stuck-at Faults},
booktitle = {13th Asian Test Symposium {(ATS} 2004), 15-17 November 2004, Kenting,
Taiwan},
pages = {178--183},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/ATS.2004.89},
doi = {10.1109/ATS.2004.89},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/YuRP04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/PomeranzR04a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {A Postprocessing Procedure of Test Enrichment for Path Delay Faults},
booktitle = {13th Asian Test Symposium {(ATS} 2004), 15-17 November 2004, Kenting,
Taiwan},
pages = {448--453},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/ATS.2004.14},
doi = {10.1109/ATS.2004.14},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/PomeranzR04a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/LiRP04,
author = {Wei Li and
Sudhakar M. Reddy and
Irith Pomeranz},
editor = {Sharad Malik and
Limor Fix and
Andrew B. Kahng},
title = {On test generation for transition faults with minimized peak power
dissipation},
booktitle = {Proceedings of the 41th Design Automation Conference, {DAC} 2004,
San Diego, CA, USA, June 7-11, 2004},
pages = {504--509},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/996566.996706},
doi = {10.1145/996566.996706},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/LiRP04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/Pomeranz04,
author = {Irith Pomeranz},
editor = {Sharad Malik and
Limor Fix and
Andrew B. Kahng},
title = {On the generation of scan-based test sets with reachable states for
testing under functional operation conditions},
booktitle = {Proceedings of the 41th Design Automation Conference, {DAC} 2004,
San Diego, CA, USA, June 7-11, 2004},
pages = {928--933},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/996566.996813},
doi = {10.1145/996566.996813},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/Pomeranz04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/Pomeranz04a,
author = {Irith Pomeranz},
editor = {Sharad Malik and
Limor Fix and
Andrew B. Kahng},
title = {Scan-BIST based on transition probabilities},
booktitle = {Proceedings of the 41th Design Automation Conference, {DAC} 2004,
San Diego, CA, USA, June 7-11, 2004},
pages = {940--943},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/996566.996815},
doi = {10.1145/996566.996815},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/Pomeranz04a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PomeranzR04,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Level of Similarity: {A} Metric for Fault Collapsing},
booktitle = {2004 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2004), 16-20 February 2004, Paris, France},
pages = {56--61},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/DATE.2004.1268827},
doi = {10.1109/DATE.2004.1268827},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/PomeranzR04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PomeranzVRS04,
author = {Irith Pomeranz and
Srikanth Venkataraman and
Sudhakar M. Reddy and
Bharath Seshadri},
title = {Z-Sets and Z-Detections: Circuit Characteristics that Simplify Fault
Diagnosis},
booktitle = {2004 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2004), 16-20 February 2004, Paris, France},
pages = {68--75},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/DATE.2004.1268829},
doi = {10.1109/DATE.2004.1268829},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/PomeranzVRS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/PomeranzR04,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Reducing Fault Latency in Concurrent On-Line Testing by Using Checking
Functions over Internal Lines},
booktitle = {19th {IEEE} International Symposium on Defect and Fault-Tolerance
in {VLSI} Systems {(DFT} 2004), 10-13 October 2004, Cannes, France,
Proceedings},
pages = {183--190},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/DFT.2004.50},
doi = {10.1109/DFT.2004.50},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dft/PomeranzR04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/PomeranzR04a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Concurrent On-Line Testing of Identical Circuits Through Output Comparison
Using Non-Identical Input Vectors},
booktitle = {19th {IEEE} International Symposium on Defect and Fault-Tolerance
in {VLSI} Systems {(DFT} 2004), 10-13 October 2004, Cannes, France,
Proceedings},
pages = {469--476},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/DFT.2004.20},
doi = {10.1109/DFT.2004.20},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dft/PomeranzR04a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/PomeranzR04,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On Undetectable Faults in Partial Scan Circuits Using Transparent-Scan},
booktitle = {22nd {IEEE} International Conference on Computer Design: {VLSI} in
Computers {\&} Processors {(ICCD} 2004), 11-13 October 2004, San
Jose, CA, USA, Proceedings},
pages = {82--84},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/ICCD.2004.1347904},
doi = {10.1109/ICCD.2004.1347904},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/PomeranzR04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/ChoPR04,
author = {Yonsang Cho and
Irith Pomeranz and
Sudhakar M. Reddy},
title = {Test Application Time Reduction for Scan Circuits Using Limited Scan
Operations},
booktitle = {5th International Symposium on Quality of Electronic Design {(ISQED}
2004), 22-24 March 2004, San Jose, CA, {USA}},
pages = {211--216},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/ISQED.2004.1283675},
doi = {10.1109/ISQED.2004.1283675},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/ChoPR04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/LeePR04,
author = {Hangkyu Lee and
Irith Pomeranz and
Sudhakar M. Reddy},
title = {Scan {BIST} Targeting Transition Faults Using a Markov Source},
booktitle = {5th International Symposium on Quality of Electronic Design {(ISQED}
2004), 22-24 March 2004, San Jose, CA, {USA}},
pages = {497--502},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/ISQED.2004.1283722},
doi = {10.1109/ISQED.2004.1283722},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/LeePR04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/PomeranzVR04,
author = {Irith Pomeranz and
Srikanth Venkataraman and
Sudhakar M. Reddy},
title = {{Z-DFD:} Design-for-Diagnosability Based on the Concept of Z-Detection},
booktitle = {Proceedings 2004 International Test Conference {(ITC} 2004), October
26-28, 2004, Charlotte, NC, {USA}},
pages = {489--497},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/TEST.2004.1386985},
doi = {10.1109/TEST.2004.1386985},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/PomeranzVR04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/PomeranzVRA04,
author = {Irith Pomeranz and
Srikanth Venkataraman and
Sudhakar M. Reddy and
M. Enamul Amyeen},
title = {Defect Diagnosis Based on Pattern-Dependent Stuck-At Faults},
booktitle = {17th International Conference on {VLSI} Design {(VLSI} Design 2004),
with the 3rd International Conference on Embedded Systems Design,
5-9 January 2004, Mumbai, India},
pages = {475--480},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/ICVD.2004.1260966},
doi = {10.1109/ICVD.2004.1260966},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/PomeranzVRA04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/PomeranzR04,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On Interconnecting Circuits with Multiple Scan Chains for Improved
Test Data Compression},
booktitle = {17th International Conference on {VLSI} Design {(VLSI} Design 2004),
with the 3rd International Conference on Embedded Systems Design,
5-9 January 2004, Mumbai, India},
pages = {741--744},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/ICVD.2004.1261016},
doi = {10.1109/ICVD.2004.1261016},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/PomeranzR04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/et/ShaoRPK03,
author = {Yun Shao and
Sudhakar M. Reddy and
Irith Pomeranz and
Seiji Kajihara},
title = {On Selecting Testable Paths in Scan Designs},
journal = {J. Electron. Test.},
volume = {19},
number = {4},
pages = {447--456},
year = {2003},
url = {https://doi.org/10.1023/A:1024648227669},
doi = {10.1023/A:1024648227669},
timestamp = {Fri, 11 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/et/ShaoRPK03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/et/BasturkmenRP03,
author = {Nadir Z. Basturkmen and
Sudhakar M. Reddy and
Irith Pomeranz},
title = {A Low Power Pseudo-Random {BIST} Technique},
journal = {J. Electron. Test.},
volume = {19},
number = {6},
pages = {637--644},
year = {2003},
url = {https://doi.org/10.1023/A:1027470721780},
doi = {10.1023/A:1027470721780},
timestamp = {Fri, 11 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/et/BasturkmenRP03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/micro/GomaaSVP03,
author = {Mohamed A. Gomaa and
Chad Scarbrough and
T. N. Vijaykumar and
Irith Pomeranz},
title = {Transient-Fault Recovery for Chip Multiprocessors},
journal = {{IEEE} Micro},
volume = {23},
number = {6},
pages = {76--83},
year = {2003},
url = {https://doi.org/10.1109/MM.2003.1261390},
doi = {10.1109/MM.2003.1261390},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/micro/GomaaSVP03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR03,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Test enrichment for path delay faults using multiple sets of target
faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {22},
number = {1},
pages = {82--90},
year = {2003},
url = {https://doi.org/10.1109/TCAD.2002.805726},
doi = {10.1109/TCAD.2002.805726},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GuoRP03,
author = {Ruifeng Guo and
Sudhakar M. Reddy and
Irith Pomeranz},
title = {Reverse-order-restoration-based static test compaction for synchronous
sequential circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {22},
number = {3},
pages = {293--304},
year = {2003},
url = {https://doi.org/10.1109/TCAD.2002.807885},
doi = {10.1109/TCAD.2002.807885},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GuoRP03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AmyeenFPB03,
author = {M. Enamul Amyeen and
W. Kent Fuchs and
Irith Pomeranz and
Vamsi Boppana},
title = {Fault equivalence identification in combinational circuits using implication
and evaluation techniques},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {22},
number = {7},
pages = {922--936},
year = {2003},
url = {https://doi.org/10.1109/TCAD.2003.814241},
doi = {10.1109/TCAD.2003.814241},
timestamp = {Tue, 16 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/AmyeenFPB03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GuoRP03a,
author = {Ruifeng Guo and
Sudhakar M. Reddy and
Irith Pomeranz},
title = {{PROPTEST:} a property-based test generator for synchronous sequential
circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {22},
number = {8},
pages = {1080--1091},
year = {2003},
url = {https://doi.org/10.1109/TCAD.2003.814953},
doi = {10.1109/TCAD.2003.814953},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GuoRP03a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR03a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Theorems for identifying undetectable faults in partial-scan circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {22},
number = {8},
pages = {1092--1097},
year = {2003},
url = {https://doi.org/10.1109/TCAD.2003.814957},
doi = {10.1109/TCAD.2003.814957},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR03a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR03b,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Test data compression based on input-output dependence},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {22},
number = {10},
pages = {1450--1455},
year = {2003},
url = {https://doi.org/10.1109/TCAD.2003.818122},
doi = {10.1109/TCAD.2003.818122},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR03b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR03c,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Transparent scan: a new approach to test generation and test compaction
for scan circuits that incorporates limited scan operations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {22},
number = {12},
pages = {1663--1670},
year = {2003},
url = {https://doi.org/10.1109/TCAD.2003.819424},
doi = {10.1109/TCAD.2003.819424},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR03c.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/ReddyMKP03,
author = {Sudhakar M. Reddy and
Kohei Miyase and
Seiji Kajihara and
Irith Pomeranz},
title = {On test data volume reduction for multiple scan chain designs},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {8},
number = {4},
pages = {460--469},
year = {2003},
url = {https://doi.org/10.1145/944027.944031},
doi = {10.1145/944027.944031},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/ReddyMKP03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/PomeranzR03,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {A {DFT} Approach for Path Delay Faults in Interconnected Circuits},
booktitle = {12th Asian Test Symposium {(ATS} 2003), 17-19 November 2003, Xian,
China},
pages = {72--77},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/ATS.2003.1250786},
doi = {10.1109/ATS.2003.1250786},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/PomeranzR03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/PomeranzR03a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Test Data Volume Reduction by Test Data Realignment},
booktitle = {12th Asian Test Symposium {(ATS} 2003), 17-19 November 2003, Xian,
China},
pages = {434--439},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/ATS.2003.1250851},
doi = {10.1109/ATS.2003.1250851},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/PomeranzR03a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/LiYRP03,
author = {Wei Li and
Chaowen Yu and
Sudhakar M. Reddy and
Irith Pomeranz},
title = {A scan {BIST} generation method using a markov source and partial
bit-fixing},
booktitle = {Proceedings of the 40th Design Automation Conference, {DAC} 2003,
Anaheim, CA, USA, June 2-6, 2003},
pages = {554--559},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/775832.775974},
doi = {10.1145/775832.775974},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/LiYRP03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/PomeranzR03,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On test data compression and n-detection test sets},
booktitle = {Proceedings of the 40th Design Automation Conference, {DAC} 2003,
Anaheim, CA, USA, June 2-6, 2003},
pages = {748--751},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/775832.776023},
doi = {10.1145/775832.776023},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/PomeranzR03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PomeranzR03,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {A New Approach to Test Generation and Test Compaction for Scan Circuits},
booktitle = {2003 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2003), 3-7 March 2003, Munich, Germany},
pages = {11000--11005},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.ieeecomputersociety.org/10.1109/DATE.2003.10002},
doi = {10.1109/DATE.2003.10002},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/PomeranzR03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PomeranzRK03,
author = {Irith Pomeranz and
Sudhakar M. Reddy and
Sandip Kundu},
title = {On the Characterization of Hard-to-Detect Bridging Faults},
booktitle = {2003 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2003), 3-7 March 2003, Munich, Germany},
pages = {11012--11019},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.ieeecomputersociety.org/10.1109/DATE.2003.10015},
doi = {10.1109/DATE.2003.10015},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/PomeranzRK03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PomeranzR03a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Test Data Compression Based on Output Dependence},
booktitle = {2003 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2003), 3-7 March 2003, Munich, Germany},
pages = {11186--11187},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.ieeecomputersociety.org/10.1109/DATE.2003.10039},
doi = {10.1109/DATE.2003.10039},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/PomeranzR03a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ets/SeshadriPRK03,
author = {Bharath Seshadri and
Irith Pomeranz and
Sudhakar M. Reddy and
Sandip Kundu},
title = {On path selection for delay fault testing considering operating conditions
[logic {IC} testing]},
booktitle = {8th European Test Workshop, {ETW} 2003, Maastricht, The Netherlands,
May 25-28, 2003},
pages = {141--146},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/ETW.2003.1231681},
doi = {10.1109/ETW.2003.1231681},
timestamp = {Tue, 28 Apr 2020 10:30:50 +0200},
biburl = {https://dblp.org/rec/conf/ets/SeshadriPRK03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/WangRPRT03,
author = {Chen Wang and
Sudhakar M. Reddy and
Irith Pomeranz and
Janusz Rajski and
Jerzy Tyszer},
title = {On Compacting Test Response Data Containing Unknown Values},
booktitle = {2003 International Conference on Computer-Aided Design, {ICCAD} 2003,
San Jose, CA, USA, November 9-13, 2003},
pages = {855--862},
publisher = {{IEEE} Computer Society / {ACM}},
year = {2003},
url = {https://doi.ieeecomputersociety.org/10.1109/ICCAD.2003.1257908},
doi = {10.1109/ICCAD.2003.1257908},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/WangRPRT03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/PomeranzR03,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On Application of Output Masking to Undetectable Faults in Synchronous
Sequential Circuits with Design-for-Testability Logic},
booktitle = {2003 International Conference on Computer-Aided Design, {ICCAD} 2003,
San Jose, CA, USA, November 9-13, 2003},
pages = {867--873},
publisher = {{IEEE} Computer Society / {ACM}},
year = {2003},
url = {https://doi.ieeecomputersociety.org/10.1109/ICCAD.2003.1257910},
doi = {10.1109/ICCAD.2003.1257910},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/PomeranzR03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/ChenRP03,
author = {Gang Chen and
Sudhakar M. Reddy and
Irith Pomeranz},
title = {Procedures for Identifying Untestable and Redundant Transition Faults
in Synchronous Sequential Circuits},
booktitle = {21st International Conference on Computer Design {(ICCD} 2003),VLSI
in Computers and Processors, 13-15 October 2003, San Jose, CA, USA,
Proceedings},
pages = {36--41},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/ICCD.2003.1240870},
doi = {10.1109/ICCD.2003.1240870},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/ChenRP03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/PomeranzR03,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Static Test Compaction for Multiple Full-Scan Circuits},
booktitle = {21st International Conference on Computer Design {(ICCD} 2003),VLSI
in Computers and Processors, 13-15 October 2003, San Jose, CA, USA,
Proceedings},
pages = {393--396},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/ICCD.2003.1240926},
doi = {10.1109/ICCD.2003.1240926},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/PomeranzR03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/HigamiKTKP03,
author = {Yoshinobu Higami and
Shin{-}ya Kobayashi and
Yuzo Takamatsu and
Seiji Kajihara and
Irith Pomeranz},
title = {A Method to Find Don't Care Values in Test Sequences for Sequential
Circuits},
booktitle = {21st International Conference on Computer Design {(ICCD} 2003),VLSI
in Computers and Processors, 13-15 October 2003, San Jose, CA, USA,
Proceedings},
pages = {397},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/ICCD.2003.1240927},
doi = {10.1109/ICCD.2003.1240927},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/HigamiKTKP03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iolts/YuLRP03,
author = {Chaowen Yu and
Wei Li and
Sudhakar M. Reddy and
Irith Pomeranz},
title = {An Improved Markov Source Design for Scan {BIST}},
booktitle = {9th {IEEE} International On-Line Testing Symposium {(IOLTS} 2003),
7-9 July 2003, Kos Island, Greece},
pages = {106--110},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/OLT.2003.1214375},
doi = {10.1109/OLT.2003.1214375},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iolts/YuLRP03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/GomaaSPV03,
author = {Mohamed A. Gomaa and
Chad Scarbrough and
Irith Pomeranz and
T. N. Vijaykumar},
editor = {Allan Gottlieb and
Kai Li},
title = {Transient-Fault Recovery for Chip Multiprocessors},
booktitle = {30th International Symposium on Computer Architecture {(ISCA} 2003),
9-11 June 2003, San Diego, California, {USA}},
pages = {98--109},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.ieeecomputersociety.org/10.1109/ISCA.2003.1206992},
doi = {10.1109/ISCA.2003.1206992},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isca/GomaaSPV03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/Pomeranz03,
author = {Irith Pomeranz},
title = {Reducing Test Data Volume Using Random-Testable and Periodic-Testable
Scan Chains in Circuits with Multiple Scan Chains},
booktitle = {Proceedings 2003 International Test Conference {(ITC} 2003), Breaking
Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte,
NC, {USA}},
pages = {441--450},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/TEST.2003.1270869},
doi = {10.1109/TEST.2003.1270869},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/Pomeranz03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/NarusePRK03,
author = {Masao Naruse and
Irith Pomeranz and
Sudhakar M. Reddy and
Sandip Kundu},
title = {On-chip Compression of Output Responses with Unknown Values Using
{LFSR} Reseeding},
booktitle = {Proceedings 2003 International Test Conference {(ITC} 2003), Breaking
Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte,
NC, {USA}},
pages = {1060--1068},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/TEST.2003.1271094},
doi = {10.1109/TEST.2003.1271094},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/NarusePRK03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/TangRP03,
author = {Huaxing Tang and
Sudhakar M. Reddy and
Irith Pomeranz},
title = {On Reducing Test Data Volume and Test Application Time for Multiple
Scan Chain Designs},
booktitle = {Proceedings 2003 International Test Conference {(ITC} 2003), Breaking
Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte,
NC, {USA}},
pages = {1079--1088},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/TEST.2003.1271096},
doi = {10.1109/TEST.2003.1271096},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/TangRP03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZouCRP03,
author = {Wei Zou and
Chris Chu and
Sudhakar M. Reddy and
Irith Pomeranz},
editor = {Manfred Glesner and
Ricardo Augusto da Luz Reis and
Hans Eveking and
Vincent John Mooney III and
Leandro Soares Indrusiak and
Peter Zipf},
title = {Optimizing {SOC} Test Resources using Dual Sequences},
booktitle = {{IFIP} VLSI-SoC 2003, {IFIP} {WG} 10.5 International Conference on
Very Large Scale Integration of System-on-Chip, Darmstadt, Germany,
1-3 December 2003},
pages = {180--185},
publisher = {Technische Universit{\"{a}}t Darmstadt, Insitute of Microelectronic
Systems},
year = {2003},
timestamp = {Wed, 12 Jan 2011 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ZouCRP03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZouCRP03a,
author = {Wei Zou and
Chris C. N. Chu and
Sudhakar M. Reddy and
Irith Pomeranz},
editor = {Manfred Glesner and
Ricardo Augusto da Luz Reis and
Leandro Soares Indrusiak and
Vincent John Mooney III and
Hans Eveking},
title = {Optimizing {SOC} Test Resources Using Dual Sequences},
booktitle = {{VLSI-SOC:} From Systems to Chips - {IFIP} {TC} 10/ {WG} 10.5 Twelfth
International Conference on Very Large Scale Integration of System
on Chip (VLSI-SoC 2003), December 1-3, 2003, Darmstadt, Germany},
series = {{IFIP}},
volume = {200},
pages = {181--196},
publisher = {Springer},
year = {2003},
url = {https://doi.org/10.1007/0-387-33403-3\_12},
doi = {10.1007/0-387-33403-3\_12},
timestamp = {Tue, 26 Jun 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ZouCRP03a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/PomeranzR03,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Static Test Compaction for Full-Scan Circuits Based on Combinational
Test Sets and Non-Scan Sequential Test Sequences},
booktitle = {16th International Conference on {VLSI} Design {(VLSI} Design 2003),
4-8 January 2003, New Delhi, India},
pages = {335--340},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/ICVD.2003.1183159},
doi = {10.1109/ICVD.2003.1183159},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/PomeranzR03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/VenkataramanRP03,
author = {Ganesh Venkataraman and
Sudhakar M. Reddy and
Irith Pomeranz},
title = {{GALLOP:} Genetic Algorithm based Low Power {FSM} Synthesis by Simultaneous
Partitioning and State Assignment},
booktitle = {16th International Conference on {VLSI} Design {(VLSI} Design 2003),
4-8 January 2003, New Delhi, India},
pages = {533--538},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/ICVD.2003.1183189},
doi = {10.1109/ICVD.2003.1183189},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/VenkataramanRP03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/PomeranzR03,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On Maximizing the Fault Coverage for a Given Test Length Limit in
a Synchronous Sequential Circuit},
booktitle = {21st {IEEE} {VLSI} Test Symposium {(VTS} 2003), 27 April - 1 May 2003,
Napa Valley, CA, {USA}},
pages = {173--178},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/VTEST.2003.1197648},
doi = {10.1109/VTEST.2003.1197648},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/PomeranzR03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/ZouRPH03,
author = {Wei Zou and
Sudhakar M. Reddy and
Irith Pomeranz and
Yu Huang},
title = {{SOC} Test Scheduling Using Simulated Annealing},
booktitle = {21st {IEEE} {VLSI} Test Symposium {(VTS} 2003), 27 April - 1 May 2003,
Napa Valley, CA, {USA}},
pages = {325--330},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/VTEST.2003.1197670},
doi = {10.1109/VTEST.2003.1197670},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/ZouRPH03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/YuAVGP03,
author = {Xiaoming Yu and
M. Enamul Amyeen and
Srikanth Venkataraman and
Ruifeng Guo and
Irith Pomeranz},
title = {Concurrent Execution of Diagnostic Fault Simulation and Equivalence
Identification During Diagnostic Test Generation},
booktitle = {21st {IEEE} {VLSI} Test Symposium {(VTS} 2003), 27 April - 1 May 2003,
Napa Valley, CA, {USA}},
pages = {351--358},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/VTEST.2003.1197674},
doi = {10.1109/VTEST.2003.1197674},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/YuAVGP03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/PomeranzRZ03,
author = {Irith Pomeranz and
Sudhakar M. Reddy and
Yervant Zorian},
title = {A Test Interface for Built-In Test of Non-Isolated Scanned Cores},
booktitle = {21st {IEEE} {VLSI} Test Symposium {(VTS} 2003), 27 April - 1 May 2003,
Napa Valley, CA, {USA}},
pages = {371--378},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/VTEST.2003.1197677},
doi = {10.1109/VTEST.2003.1197677},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/PomeranzRZ03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/PomeranzR02,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Built-In Test Sequence Generation for Synchronous Sequential Circuits
Based on Loading and Expansion of Input Sequences Using Single and
Multiple Fault Detection Times},
journal = {{IEEE} Trans. Computers},
volume = {51},
number = {4},
pages = {409--419},
year = {2002},
url = {https://doi.org/10.1109/12.995451},
doi = {10.1109/12.995451},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/PomeranzR02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/PomeranzR02a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Enumeration of Test Sequences in Increasing Chronological Order to
Improve the Levels of Compaction Achieved by Vector Omission},
journal = {{IEEE} Trans. Computers},
volume = {51},
number = {7},
pages = {866--872},
year = {2002},
url = {https://doi.org/10.1109/TC.2002.1017705},
doi = {10.1109/TC.2002.1017705},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/PomeranzR02a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/PomeranzR02b,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {A Storage-Based Built-In Test Pattern Generation Method for Scan Circuits
Based on Partitioning and Reduction of a Precomputed Test Set},
journal = {{IEEE} Trans. Computers},
volume = {51},
number = {11},
pages = {1282--1293},
year = {2002},
url = {https://doi.org/10.1109/TC.2002.1047753},
doi = {10.1109/TC.2002.1047753},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/PomeranzR02b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR02,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Property-based test generation for scan designs and the effects ofthe
test application scheme and scan selection on the number ofdetectable
faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {5},
pages = {628--637},
year = {2002},
url = {https://doi.org/10.1109/43.998633},
doi = {10.1109/43.998633},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR02a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Test compaction for at-speed testing of scan circuits based onnonscan
test. sequences and removal of transfer sequences},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {6},
pages = {706--714},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.1004314},
doi = {10.1109/TCAD.2002.1004314},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR02a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR02b,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {n-pass n-detection fault simulation and its applications},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {8},
pages = {980--986},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.800453},
doi = {10.1109/TCAD.2002.800453},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR02b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz02,
author = {Irith Pomeranz},
title = {On the use of random limited-scan to improve at-speed randompattern
testing of scan circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {9},
pages = {1068--1076},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.801092},
doi = {10.1109/TCAD.2002.801092},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/ShaoPR02,
author = {Yun Shao and
Irith Pomeranz and
Sudhakar M. Reddy},
title = {On Generating High Quality Tests for Transition Faults},
booktitle = {11th Asian Test Symposium {(ATS} 2002), 18-20 November 2002, Guam,
{USA}},
pages = {1},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/ATS.2002.1181676},
doi = {10.1109/ATS.2002.1181676},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/ShaoPR02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/PolianPB02,
author = {Ilia Polian and
Irith Pomeranz and
Bernd Becker},
title = {Exact Computation of Maximally Dominating Faults and Its Application
to n-Detection Tests},
booktitle = {11th Asian Test Symposium {(ATS} 2002), 18-20 November 2002, Guam,
{USA}},
pages = {2--14},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/ATS.2002.1181677},
doi = {10.1109/ATS.2002.1181677},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/PolianPB02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/PomeranzR02,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Improving the Efficiency of Static Compaction Based on Chronological
Order Enumeration of Test Sequences},
booktitle = {11th Asian Test Symposium {(ATS} 2002), 18-20 November 2002, Guam,
{USA}},
pages = {61--66},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/ATS.2002.1181686},
doi = {10.1109/ATS.2002.1181686},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/PomeranzR02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/KajiharaTMPR02,
author = {Seiji Kajihara and
Kenjiro Taniguchi and
Kohei Miyase and
Irith Pomeranz and
Sudhakar M. Reddy},
title = {Test Data Compression Using Don?t-Care Identification and Statistical
Encoding},
booktitle = {11th Asian Test Symposium {(ATS} 2002), 18-20 November 2002, Guam,
{USA}},
pages = {67},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/ATS.2002.1181687},
doi = {10.1109/ATS.2002.1181687},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/KajiharaTMPR02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/PomeranzR02a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {A Partitioning and Storage Based Built-In Test Pattern Generation
Method for Delay Faults in Scan Circuits},
booktitle = {11th Asian Test Symposium {(ATS} 2002), 18-20 November 2002, Guam,
{USA}},
pages = {110--115},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/ATS.2002.1181696},
doi = {10.1109/ATS.2002.1181696},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/PomeranzR02a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/PomeranzKR02,
author = {Irith Pomeranz and
Sandip Kundu and
Sudhakar M. Reddy},
title = {On output response compression in the presence of unknown output values},
booktitle = {Proceedings of the 39th Design Automation Conference, {DAC} 2002,
New Orleans, LA, USA, June 10-14, 2002},
pages = {255--258},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/513918.513985},
doi = {10.1145/513918.513985},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/PomeranzKR02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PomeranzR02,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Test Enrichment for Path Delay Faults Using Multiple Sets of Target
Faults},
booktitle = {2002 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2002), 4-8 March 2002, Paris, France},
pages = {722--729},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/DATE.2002.998379},
doi = {10.1109/DATE.2002.998379},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/PomeranzR02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PomeranzRR02,
author = {Irith Pomeranz and
Janusz Rajski and
Sudhakar M. Reddy},
title = {Finding a Common Fault Response for Diagnosis during Silicon Debug},
booktitle = {2002 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2002), 4-8 March 2002, Paris, France},
pages = {1116},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/DATE.2002.998471},
doi = {10.1109/DATE.2002.998471},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/PomeranzRR02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PomeranzZ02,
author = {Irith Pomeranz and
Yervant Zorian},
title = {Fault Isolation Using Tests for Non-Isolated Blocks},
booktitle = {2002 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2002), 4-8 March 2002, Paris, France},
pages = {1123},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/DATE.2002.998479},
doi = {10.1109/DATE.2002.998479},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/PomeranzZ02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/delta/PomeranzR02,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Properties of Output Sequences and their Use in Guiding Property-Based
Test Generation for Synchronous Sequential Circuits},
booktitle = {1st {IEEE} International Workshop on Electronic Design, Test and Applications
{(DELTA} 2002), 29-31 January 2002, Christchurch, New Zealand},
pages = {377--381},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/DELTA.2002.994654},
doi = {10.1109/DELTA.2002.994654},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/delta/PomeranzR02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/delta/KajiharaTPR02,
author = {Seiji Kajihara and
Kenjiro Taniguchi and
Irith Pomeranz and
Sudhakar M. Reddy},
title = {Test Data Compression Using Don't-Care Identification and Statistical
Encoding},
booktitle = {1st {IEEE} International Workshop on Electronic Design, Test and Applications
{(DELTA} 2002), 29-31 January 2002, Christchurch, New Zealand},
pages = {413--416},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/DELTA.2002.994661},
doi = {10.1109/DELTA.2002.994661},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/delta/KajiharaTPR02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ets/ShaoRPK02,
author = {Yun Shao and
Sudhakar M. Reddy and
Irith Pomeranz and
Seiji Kajihara},
title = {On selecting testable paths in scan designs},
booktitle = {7th European Test Workshop, {ETW} 2002, Corfu, Greece, May 26-29,
2002},
pages = {53--58},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/ETW.2002.1029639},
doi = {10.1109/ETW.2002.1029639},
timestamp = {Tue, 28 Apr 2020 10:30:50 +0200},
biburl = {https://dblp.org/rec/conf/ets/ShaoRPK02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/PomeranzR02,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Lawrence T. Pileggi and
Andreas Kuehlmann},
title = {On undetectable faults in partial scan circuits},
booktitle = {Proceedings of the 2002 {IEEE/ACM} International Conference on Computer-aided
Design, {ICCAD} 2002, San Jose, California, USA, November 10-14, 2002},
pages = {82--86},
publisher = {{ACM} / {IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1145/774572.774584},
doi = {10.1145/774572.774584},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/PomeranzR02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/WangRPLR02,
author = {Chen Wang and
Sudhakar M. Reddy and
Irith Pomeranz and
Xijiang Lin and
Janusz Rajski},
editor = {Lawrence T. Pileggi and
Andreas Kuehlmann},
title = {Conflict driven techniques for improving deterministic test pattern
generation},
booktitle = {Proceedings of the 2002 {IEEE/ACM} International Conference on Computer-aided
Design, {ICCAD} 2002, San Jose, California, USA, November 10-14, 2002},
pages = {87--93},
publisher = {{ACM} / {IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1145/774572.774585},
doi = {10.1145/774572.774585},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/WangRPLR02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/MiyaseKPR02,
author = {Kohei Miyase and
Seiji Kajihara and
Irith Pomeranz and
Sudhakar M. Reddy},
title = {Don't-Care Identification on Specific Bits of Test Patterns},
booktitle = {20th International Conference on Computer Design {(ICCD} 2002), {VLSI}
in Computers and Processors, 16-18 September 2002, Freiburg, Germany,
Proceedings},
pages = {194--199},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/ICCD.2002.1106769},
doi = {10.1109/ICCD.2002.1106769},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/MiyaseKPR02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/PomeranzR02,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On the Coverage of Delay Faults in Scan Designs with Multiple Scan
Chains},
booktitle = {20th International Conference on Computer Design {(ICCD} 2002), {VLSI}
in Computers and Processors, 16-18 September 2002, Freiburg, Germany,
Proceedings},
pages = {206--209},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/ICCD.2002.1106771},
doi = {10.1109/ICCD.2002.1106771},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/PomeranzR02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/BasturkmenRP02,
author = {Nadir Z. Basturkmen and
Sudhakar M. Reddy and
Irith Pomeranz},
title = {A Low Power Pseudo-Random {BIST} Technique},
booktitle = {20th International Conference on Computer Design {(ICCD} 2002), {VLSI}
in Computers and Processors, 16-18 September 2002, Freiburg, Germany,
Proceedings},
pages = {468--473},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/ICCD.2002.1106815},
doi = {10.1109/ICCD.2002.1106815},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/BasturkmenRP02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iolts/BasturkmenRP02,
author = {Nadir Z. Basturkmen and
Sudhakar M. Reddy and
Irith Pomeranz},
title = {A Low Power Pseudo-Random {BIST} Technique},
booktitle = {8th {IEEE} International On-Line Testing Workshop {(IOLTW} 2002),
8-10 July 2002, Isle of Bendor, France},
pages = {140},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/OLT.2002.1030197},
doi = {10.1109/OLT.2002.1030197},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iolts/BasturkmenRP02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/VijaykumarPC02,
author = {T. N. Vijaykumar and
Irith Pomeranz and
Karl Cheng},
editor = {Yale N. Patt and
Dirk Grunwald and
Kevin Skadron},
title = {Transient-Fault Recovery Using Simultaneous Multithreading},
booktitle = {29th International Symposium on Computer Architecture {(ISCA} 2002),
25-29 May 2002, Anchorage, AK, {USA}},
pages = {87--98},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/ISCA.2002.1003565},
doi = {10.1109/ISCA.2002.1003565},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isca/VijaykumarPC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/ReddyPTKK02,
author = {Sudhakar M. Reddy and
Irith Pomeranz and
Huaxing Tang and
Seiji Kajihara and
Kozo Kinoshita},
title = {On Testing of Interconnect Open Defects in Combinational Logic Circuits
with Stems of Large Fanout},
booktitle = {Proceedings {IEEE} International Test Conference 2002, Baltimore,
MD, USA, October 7-10, 2002},
pages = {83--89},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/TEST.2002.1041748},
doi = {10.1109/TEST.2002.1041748},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/ReddyPTKK02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/BasturkmenRP02,
author = {Nadir Z. Basturkmen and
Sudhakar M. Reddy and
Irith Pomeranz},
title = {Pseudo Random Patterns Using Markov Sources for Scan {BIST}},
booktitle = {Proceedings {IEEE} International Test Conference 2002, Baltimore,
MD, USA, October 7-10, 2002},
pages = {1013--1021},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/TEST.2002.1041857},
doi = {10.1109/TEST.2002.1041857},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/BasturkmenRP02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/PomeranzR02,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {A Partitioning and Storage Based Built-In Test Pattern Generation
Method for Scan Circuits},
booktitle = {Proceedings of the 7th Asia and South Pacific Design Automation Conference
{(ASP-DAC} 2002), and the 15th International Conference on {VLSI}
Design {(VLSI} Design 2002), Bangalore, India, January 7-11, 2002},
pages = {677--682},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/ASPDAC.2002.995013},
doi = {10.1109/ASPDAC.2002.995013},
timestamp = {Mon, 14 Nov 2022 15:28:09 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/PomeranzR02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/ShaoPR02,
author = {Yun Shao and
Irith Pomeranz and
Sudhakar M. Reddy},
title = {Path Delay Fault Test Generation for Standard Scan Designs Using State
Tuples},
booktitle = {Proceedings of the 7th Asia and South Pacific Design Automation Conference
{(ASP-DAC} 2002), and the 15th International Conference on {VLSI}
Design {(VLSI} Design 2002), Bangalore, India, January 7-11, 2002},
pages = {767--772},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/ASPDAC.2002.995026},
doi = {10.1109/ASPDAC.2002.995026},
timestamp = {Mon, 14 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/ShaoPR02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/ReddyMKP02,
author = {Sudhakar M. Reddy and
Kohei Miyase and
Seiji Kajihara and
Irith Pomeranz},
title = {On Test Data Volume Reduction for Multiple Scan Chain Designs},
booktitle = {20th {IEEE} {VLSI} Test Symposium {(VTS} 2002), Without Testing It's
a Gamble, 28 April - 2 May 2002, Monterey, CA, {USA}},
pages = {103--110},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/VTS.2002.1011119},
doi = {10.1109/VTS.2002.1011119},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/ReddyMKP02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/AmyeenPF02,
author = {M. Enamul Amyeen and
Irith Pomeranz and
W. Kent Fuchs},
title = {Theorems for Efficient Identification of Indistinguishable Fault Pairs
in Synchronous Sequential Circuits},
booktitle = {20th {IEEE} {VLSI} Test Symposium {(VTS} 2002), Without Testing It's
a Gamble, 28 April - 2 May 2002, Monterey, CA, {USA}},
pages = {181--186},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/VTS.2002.1011136},
doi = {10.1109/VTS.2002.1011136},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/AmyeenPF02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/PomeranzR01,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Design-for-testability to achieve complete coverage of delay faults
in standard full scan circuits},
journal = {J. Syst. Archit.},
volume = {47},
number = {3-4},
pages = {357--373},
year = {2001},
url = {https://doi.org/10.1016/S1383-7621(00)00054-0},
doi = {10.1016/S1383-7621(00)00054-0},
timestamp = {Tue, 19 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jsa/PomeranzR01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR01,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Vector replacement to improve static-test compaction forsynchronous
sequential circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {2},
pages = {336--342},
year = {2001},
url = {https://doi.org/10.1109/43.908476},
doi = {10.1109/43.908476},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR01a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On diagnosis and diagnostic test generation for pattern-dependenttransition
faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {6},
pages = {791--800},
year = {2001},
url = {https://doi.org/10.1109/43.924832},
doi = {10.1109/43.924832},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR01a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzZ01,
author = {Irith Pomeranz and
Y. Zonan},
title = {Testing of scan circuits containing nonisolated random-logic legacycores},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {8},
pages = {980--993},
year = {2001},
url = {https://doi.org/10.1109/43.936379},
doi = {10.1109/43.936379},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzZ01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR01b,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Forward-looking fault simulation for improved static compaction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {10},
pages = {1262--1265},
year = {2001},
url = {https://doi.org/10.1109/43.952743},
doi = {10.1109/43.952743},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR01b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PomeranzR01,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {A built-in self-test method for diagnosis of synchronous sequential
circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {9},
number = {2},
pages = {290--296},
year = {2001},
url = {https://doi.org/10.1109/92.924046},
doi = {10.1109/92.924046},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PomeranzR01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PomeranzR01a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Resynthesis of combinational logic circuits for improved path delay
fault testability using comparison units},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {9},
number = {5},
pages = {679--689},
year = {2001},
url = {https://doi.org/10.1109/92.953501},
doi = {10.1109/92.953501},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PomeranzR01a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/Pomeranz01,
author = {Irith Pomeranz},
title = {On Pass/Fail Dictionaries for Scan Circuits},
booktitle = {10th Asian Test Symposium {(ATS} 2001), 19-21 November 2001, Kyoto,
Japan},
pages = {51--56},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/ATS.2001.990258},
doi = {10.1109/ATS.2001.990258},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/Pomeranz01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/GuoRP01,
author = {Ruifeng Guo and
Sudhakar M. Reddy and
Irith Pomeranz},
title = {On Improving a Fault Simulation Based Test Generator for Synchronous
Sequential Circuits},
booktitle = {10th Asian Test Symposium {(ATS} 2001), 19-21 November 2001, Kyoto,
Japan},
pages = {82},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/ATS.2001.990264},
doi = {10.1109/ATS.2001.990264},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/GuoRP01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/PomeranzR01,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {A Postprocessing Procedure to Reduce the Number of Different Test
Lengths in a Test Set for Scan Circuits},
booktitle = {10th Asian Test Symposium {(ATS} 2001), 19-21 November 2001, Kyoto,
Japan},
pages = {131--136},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/ATS.2001.990271},
doi = {10.1109/ATS.2001.990271},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/PomeranzR01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/ShaoRKP01,
author = {Yun Shao and
Sudhakar M. Reddy and
Seiji Kajihara and
Irith Pomeranz},
title = {An Efficient Method to Identify Untestable Path Delay Faults},
booktitle = {10th Asian Test Symposium {(ATS} 2001), 19-21 November 2001, Kyoto,
Japan},
pages = {233--238},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/ATS.2001.990287},
doi = {10.1109/ATS.2001.990287},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/ShaoRKP01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/PomeranzRL01,
author = {Irith Pomeranz and
Sudhakar M. Reddy and
Xijiang Lin},
title = {Experimental Results of Forward-Looking Reverse Order Fault Simulation
on Industrial Circuits with Scan},
booktitle = {10th Asian Test Symposium {(ATS} 2001), 19-21 November 2001, Kyoto,
Japan},
pages = {467},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/ATS.2001.990334},
doi = {10.1109/ATS.2001.990334},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/PomeranzRL01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/Pomeranz01,
author = {Irith Pomeranz},
title = {Random Limited-Scan to Improve Random Pattern Testing of Scan Circuits},
booktitle = {Proceedings of the 38th Design Automation Conference, {DAC} 2001,
Las Vegas, NV, USA, June 18-22, 2001},
pages = {145--150},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/378239.378385},
doi = {10.1145/378239.378385},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/Pomeranz01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/PomeranzR01,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {An Approach to Test Compaction for Scan Circuits that Enhances At-Speed
Testing},
booktitle = {Proceedings of the 38th Design Automation Conference, {DAC} 2001,
Las Vegas, NV, USA, June 18-22, 2001},
pages = {156--161},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/378239.378390},
doi = {10.1145/378239.378390},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/PomeranzR01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PomeranzR01,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Wolfgang Nebel and
Ahmed Jerraya},
title = {Sequence reordering to improve the levels of compaction achievable
by static compaction procedures},
booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe,
{DATE} 2001, Munich, Germany, March 12-16, 2001},
pages = {214--218},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/DATE.2001.915027},
doi = {10.1109/DATE.2001.915027},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/PomeranzR01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PomeranzR01a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Wolfgang Nebel and
Ahmed Jerraya},
title = {Definitions of the numbers of detections of target faults and their
effectiveness in guiding test generation for high defect coverage},
booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe,
{DATE} 2001, Munich, Germany, March 12-16, 2001},
pages = {504--508},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/DATE.2001.915070},
doi = {10.1109/DATE.2001.915070},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/PomeranzR01a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/PomeranzR01,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Kaushik Roy and
Sung{-}Mo Kang and
Cheng{-}Kok Koh},
title = {{ITEM:} an iterative improvement test generation procedure for synchronous
sequential circuits},
booktitle = {Proceedings of the 11th {ACM} Great Lakes Symposium on {VLSI} 2001,
West Lafayette, Indiana, USA, 2001},
pages = {13--18},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/368122.368147},
doi = {10.1145/368122.368147},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/PomeranzR01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hldvt/PomeranzR01,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Estimating the relative single stuck-at fault coverage of test sets
for a combinational logic block from its functional description},
booktitle = {Proceedings of the Sixth {IEEE} International High-Level Design Validation
and Test Workshop 2001, Monterey, California, USA, November 7-9, 2001},
pages = {31--35},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/HLDVT.2001.972804},
doi = {10.1109/HLDVT.2001.972804},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hldvt/PomeranzR01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/WangPR01,
author = {Chen Wang and
Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Rolf Ernst},
title = {{REDI:} An Efficient Fault Oriented Procedure to Identify Redundant
Faults in Combinational Logic Circuits},
booktitle = {Proceedings of the 2001 {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 2001, San Jose, CA, USA, November 4-8, 2001},
pages = {370--374},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/ICCAD.2001.968649},
doi = {10.1109/ICCAD.2001.968649},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/WangPR01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/PomeranzR01,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {{COREL:} {A} Dynamic Compaction Procedure for Synchronous Sequential
Circuits with Repetition and Local Static Compaction},
booktitle = {19th International Conference on Computer Design {(ICCD} 2001), {VLSI}
in Computers and Processors, 23-26 September 2001, Austin, TX, USA,
Proceedings},
pages = {142--147},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/ICCD.2001.955016},
doi = {10.1109/ICCD.2001.955016},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/PomeranzR01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/PomeranzR01a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {A Partitioning and Storage Based Built-in Test Pattern Generation
Method for Synchronous Sequential Circuits},
booktitle = {19th International Conference on Computer Design {(ICCD} 2001), {VLSI}
in Computers and Processors, 23-26 September 2001, Austin, TX, USA,
Proceedings},
pages = {148--153},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/ICCD.2001.955017},
doi = {10.1109/ICCD.2001.955017},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/PomeranzR01a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/PomeranzR01,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {A method to enhance the fault coverage obtained by output response
comparison of identical circuits},
booktitle = {Proceedings {IEEE} International Test Conference 2001, Baltimore,
MD, USA, 30 October - 1 November 2001},
pages = {196--203},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/TEST.2001.966634},
doi = {10.1109/TEST.2001.966634},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/PomeranzR01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/PomeranzR01a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On improving the stuck-at fault coverage of functional test sequences
by using limited-scan operations},
booktitle = {Proceedings {IEEE} International Test Conference 2001, Baltimore,
MD, USA, 30 October - 1 November 2001},
pages = {211--220},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/TEST.2001.966636},
doi = {10.1109/TEST.2001.966636},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/PomeranzR01a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/LinRPR01,
author = {Xijiang Lin and
Janusz Rajski and
Irith Pomeranz and
Sudhakar M. Reddy},
title = {On static test compaction and test pattern ordering for scan designs},
booktitle = {Proceedings {IEEE} International Test Conference 2001, Baltimore,
MD, USA, 30 October - 1 November 2001},
pages = {1088--1097},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/TEST.2001.966735},
doi = {10.1109/TEST.2001.966735},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/LinRPR01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/GuoPR01,
author = {Ruifeng Guo and
Irith Pomeranz and
Sudhakar M. Reddy},
title = {On Improving Static Test Compaction for Sequential Circuits},
booktitle = {14th International Conference on {VLSI} Design {(VLSI} Design 2001),
3-7 January 2001, Bangalore, India},
pages = {111--116},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/ICVD.2001.902648},
doi = {10.1109/ICVD.2001.902648},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/GuoPR01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/AmyeenFPB01,
author = {M. Enamul Amyeen and
W. Kent Fuchs and
Irith Pomeranz and
Vamsi Boppana},
title = {Fault Equivalence Identification Using Redundancy Information and
Static and Dynamic Extraction},
booktitle = {19th {IEEE} {VLSI} Test Symposium {(VTS} 2001), Test and Diagnosis
in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA,
{USA}},
pages = {124--130},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/VTS.2001.923428},
doi = {10.1109/VTS.2001.923428},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/AmyeenFPB01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/PomeranzR01,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On the Use of Fault Dominance in n-Detection Test Generation},
booktitle = {19th {IEEE} {VLSI} Test Symposium {(VTS} 2001), Test and Diagnosis
in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA,
{USA}},
pages = {352--357},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/VTS.2001.923462},
doi = {10.1109/VTS.2001.923462},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/PomeranzR01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/et/PomeranzR00,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Static Test Compaction for Scan-Based Designs to Reduce Test Application
Time},
journal = {J. Electron. Test.},
volume = {16},
number = {5},
pages = {541--552},
year = {2000},
url = {https://doi.org/10.1023/A:1008385125818},
doi = {10.1023/A:1008385125818},
timestamp = {Fri, 11 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/et/PomeranzR00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/PomeranzR00,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On Finding a Minimal Functional Description of a Finite-State Machine
for Test Generation for Adjacent Machines},
journal = {{IEEE} Trans. Computers},
volume = {49},
number = {1},
pages = {88--94},
year = {2000},
url = {https://doi.org/10.1109/12.822567},
doi = {10.1109/12.822567},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/PomeranzR00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/PomeranzR00a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On the Use of Fully Specified Initial States for Testing of Synchronous
Sequential Circuits},
journal = {{IEEE} Trans. Computers},
volume = {49},
number = {2},
pages = {175--181},
year = {2000},
url = {https://doi.org/10.1109/12.833114},
doi = {10.1109/12.833114},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/PomeranzR00a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/PomeranzR00b,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Procedures for Static Compaction of Test Sequences for Synchronous
Sequential Circuits},
journal = {{IEEE} Trans. Computers},
volume = {49},
number = {6},
pages = {596--607},
year = {2000},
url = {https://doi.org/10.1109/12.862219},
doi = {10.1109/12.862219},
timestamp = {Wed, 06 Sep 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/PomeranzR00b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR00,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On n-detection test sets and variable n-detection test sets fortransition
faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {19},
number = {3},
pages = {372--383},
year = {2000},
url = {https://doi.org/10.1109/43.833205},
doi = {10.1109/43.833205},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR00a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {A diagnostic test generation procedure based on test elimination byvector
omission for synchronous sequential circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {19},
number = {5},
pages = {589--600},
year = {2000},
url = {https://doi.org/10.1109/43.845083},
doi = {10.1109/43.845083},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR00a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR00b,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On synchronizable circuits and their synchronizing sequences},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {19},
number = {9},
pages = {1086--1092},
year = {2000},
url = {https://doi.org/10.1109/43.863649},
doi = {10.1109/43.863649},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR00b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/PomeranzR00,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On the feasibility of fault simulation using partial circuit descriptions},
booktitle = {9th Asian Test Symposium {(ATS} 2000), 4-6 December 2000, Taipei,
Taiwan},
pages = {108--113},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/ATS.2000.893611},
doi = {10.1109/ATS.2000.893611},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/PomeranzR00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/KajiharaSPR00,
author = {Seiji Kajihara and
Takashi Shimono and
Irith Pomeranz and
Sudhakar M. Reddy},
title = {Enhanced untestable path analysis using edge graphs},
booktitle = {9th Asian Test Symposium {(ATS} 2000), 4-6 December 2000, Taipei,
Taiwan},
pages = {139--144},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/ATS.2000.893616},
doi = {10.1109/ATS.2000.893616},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/KajiharaSPR00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/PomeranzR00a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Reducing test application time for full scan circuits by the addition
of transfer sequences},
booktitle = {9th Asian Test Symposium {(ATS} 2000), 4-6 December 2000, Taipei,
Taiwan},
pages = {317--322},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/ATS.2000.893643},
doi = {10.1109/ATS.2000.893643},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/PomeranzR00a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/PomeranzR00,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Giovanni De Micheli},
title = {On diagnosis of pattern-dependent delay faults},
booktitle = {Proceedings of the 37th Conference on Design Automation, Los Angeles,
CA, USA, June 5-9, 2000},
pages = {59--62},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/337292.337312},
doi = {10.1145/337292.337312},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/PomeranzR00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PomeranzR00,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Ivo Bolsens},
title = {Built-In Generation of Weighted Test Sequences for Synchronous Sequential
Circuits},
booktitle = {2000 Design, Automation and Test in Europe {(DATE} 2000), 27-30 March
2000, Paris, France},
pages = {298--304},
publisher = {{IEEE} Computer Society / {ACM}},
year = {2000},
url = {https://doi.org/10.1109/DATE.2000.840287},
doi = {10.1109/DATE.2000.840287},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/PomeranzR00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PomeranzR00a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Ivo Bolsens},
title = {Functional Test Generation for Full Scan Circuits},
booktitle = {2000 Design, Automation and Test in Europe {(DATE} 2000), 27-30 March
2000, Paris, France},
pages = {396--401},
publisher = {{IEEE} Computer Society / {ACM}},
year = {2000},
url = {https://doi.org/10.1109/DATE.2000.840302},
doi = {10.1109/DATE.2000.840302},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/PomeranzR00a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsn/PomeranzR00,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Test-Point Insertion to Enhance Test Compaction for Scan Designs},
booktitle = {2000 International Conference on Dependable Systems and Networks {(DSN}
2000) (formerly {FTCS-30} and DCCA-8), 25-28 June 2000, New York,
NY, {USA}},
pages = {375--381},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/ICDSN.2000.857564},
doi = {10.1109/ICDSN.2000.857564},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsn/PomeranzR00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ets/PomeranzR00,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On the use of multiple fault detection times in a method for built-in
test pattern generation for synchronous sequential circuits},
booktitle = {5th European Test Workshop, {ETW} 2000, Cascais, Portugal, May 23-26,
2000},
pages = {144--149},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/ETW.2000.873792},
doi = {10.1109/ETW.2000.873792},
timestamp = {Tue, 28 Apr 2020 13:03:46 +0200},
biburl = {https://dblp.org/rec/conf/ets/PomeranzR00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/HuangPRR00,
author = {Yu Huang and
Irith Pomeranz and
Sudhakar M. Reddy and
Janusz Rajski},
editor = {Ellen Sentovich},
title = {Improving the Proportion of At-Speed Tests in Scan {BIST}},
booktitle = {Proceedings of the 2000 {IEEE/ACM} International Conference on Computer-Aided
Design, 2000, San Jose, California, USA, November 5-9, 2000},
pages = {459--463},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/ICCAD.2000.896514},
doi = {10.1109/ICCAD.2000.896514},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/HuangPRR00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/PomeranzR00,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Ellen Sentovich},
title = {Simulation Based Test Generation for Scan Designs},
booktitle = {Proceedings of the 2000 {IEEE/ACM} International Conference on Computer-Aided
Design, 2000, San Jose, California, USA, November 5-9, 2000},
pages = {544--549},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/ICCAD.2000.896529},
doi = {10.1109/ICCAD.2000.896529},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/PomeranzR00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/PomeranzR00,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Sensitivity Levels of Test Patterns and Their Usefulness in Simulation-Based
Test Generation},
booktitle = {Proceedings of the {IEEE} International Conference On Computer Design:
{VLSI} In Computers {\&} Processors, {ICCD} '00, Austin, Texas,
USA, September 17-20, 2000},
pages = {389--394},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/ICCD.2000.878313},
doi = {10.1109/ICCD.2000.878313},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/PomeranzR00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/PomeranzR00a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On Test Application Time and Defect Detection Capabilities of Test
Sets for Scan Designs},
booktitle = {Proceedings of the {IEEE} International Conference On Computer Design:
{VLSI} In Computers {\&} Processors, {ICCD} '00, Austin, Texas,
USA, September 17-20, 2000},
pages = {395--400},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/ICCD.2000.878314},
doi = {10.1109/ICCD.2000.878314},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/PomeranzR00a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/ReddyPKMTO00,
author = {Sudhakar M. Reddy and
Irith Pomeranz and
Seiji Kajihara and
Atsushi Murakami and
Sadami Takeoka and
Mitsuyasu Ohta},
title = {On validating data hold times for flip-flops in sequential circuits},
booktitle = {Proceedings {IEEE} International Test Conference 2000, Atlantic City,
NJ, USA, October 2000},
pages = {317--325},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/TEST.2000.894220},
doi = {10.1109/TEST.2000.894220},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/ReddyPKMTO00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/MurakamiKSPR00,
author = {Atsushi Murakami and
Seiji Kajihara and
Tsutomu Sasao and
Irith Pomeranz and
Sudhakar M. Reddy},
title = {Selection of potentially testable path delay faults for test generation},
booktitle = {Proceedings {IEEE} International Test Conference 2000, Atlantic City,
NJ, USA, October 2000},
pages = {376--384},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/TEST.2000.894227},
doi = {10.1109/TEST.2000.894227},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/MurakamiKSPR00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/prdc/PomeranzR00,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Fault diagnosis based on parameters of output responses},
booktitle = {2000 Pacific Rim International Symposium on Dependable Computing {(PRDC}
2000), 18-20 December 2000, Los Angeles, CA, {USA}},
pages = {139--147},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/PRDC.2000.897296},
doi = {10.1109/PRDC.2000.897296},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/prdc/PomeranzR00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/IchiharaKPR00,
author = {Hideyuki Ichihara and
Kozo Kinoshita and
Irith Pomeranz and
Sudhakar M. Reddy},
title = {Test Transformation to Improve Compaction by Statistical Encoding},
booktitle = {13th International Conference on {VLSI} Design {(VLSI} Design 2000),
4-7 January 2000, Calcutta, India},
pages = {294--299},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/ICVD.2000.812624},
doi = {10.1109/ICVD.2000.812624},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/IchiharaKPR00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/PomeranzR00,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On Synchronizing Sequences and Unspecified Values in Output Responses
of Synchronous Sequential Circuits},
booktitle = {13th International Conference on {VLSI} Design {(VLSI} Design 2000),
4-7 January 2000, Calcutta, India},
pages = {392--397},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/ICVD.2000.812639},
doi = {10.1109/ICVD.2000.812639},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/PomeranzR00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/LinCPR00,
author = {Xijiang Lin and
Wu{-}Tung Cheng and
Irith Pomeranz and
Sudhakar M. Reddy},
title = {{SIFAR:} Static Test Compaction for Synchronous Sequential Circuits
Based on Single Fault Restoration},
booktitle = {18th {IEEE} {VLSI} Test Symposium {(VTS} 2000), 30 April - 4 May 2000,
Montreal, Canada},
pages = {205--212},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/VTEST.2000.843847},
doi = {10.1109/VTEST.2000.843847},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/LinCPR00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/PomeranzR99,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {A Cone-Based Genetic Optimization Procedure for Test Generation and
Its Application to n-Detections in Combinational Circuits},
journal = {{IEEE} Trans. Computers},
volume = {48},
number = {10},
pages = {1145--1152},
year = {1999},
url = {https://doi.org/10.1109/12.805164},
doi = {10.1109/12.805164},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/PomeranzR99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR99,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {A comment on "Improving a nonenumerative method to estimate path
delay fault coverage"},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {5},
pages = {665--666},
year = {1999},
url = {https://doi.org/10.1109/43.759083},
doi = {10.1109/43.759083},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzRG99,
author = {Irith Pomeranz and
Sudhakar M. Reddy and
Ruifeng Guo},
title = {Static test compaction for synchronous sequential circuits based on
vector restoration},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {18},
number = {7},
pages = {1040--1049},
year = {1999},
url = {https://doi.org/10.1109/43.771184},
doi = {10.1109/43.771184},
timestamp = {Tue, 16 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzRG99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/PomeranzR99,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Vector-Based Functional Fault Models for Delay Faults},
booktitle = {8th Asian Test Symposium {(ATS} '99), 16-18 November 1999, Shanghai,
China},
pages = {41--46},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/ATS.1999.810727},
doi = {10.1109/ATS.1999.810727},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/PomeranzR99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/PomeranzR99a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Pattern Sensitivity: {A} Property to Guide Test Generation for Combinational
Circuits},
booktitle = {8th Asian Test Symposium {(ATS} '99), 16-18 November 1999, Shanghai,
China},
pages = {75--80},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/ATS.1999.810732},
doi = {10.1109/ATS.1999.810732},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/PomeranzR99a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/GuoRP99,
author = {Ruifeng Guo and
Sudhakar M. Reddy and
Irith Pomeranz},
editor = {Mary Jane Irwin},
title = {Proptest: {A} Property Based Test Pattern Generator for Sequential
Circuits Using Test Compaction},
booktitle = {Proceedings of the 36th Conference on Design Automation, New Orleans,
LA, USA, June 21-25, 1999},
pages = {653--659},
publisher = {{ACM} Press},
year = {1999},
url = {https://doi.org/10.1145/309847.310019},
doi = {10.1145/309847.310019},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/GuoRP99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/PomeranzR99,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Mary Jane Irwin},
title = {Built-In Test Sequence Generation for Synchronous Sequential Circuits
Based on Loading and Expansion of Test Subsequences},
booktitle = {Proceedings of the 36th Conference on Design Automation, New Orleans,
LA, USA, June 21-25, 1999},
pages = {754--759},
publisher = {{ACM} Press},
year = {1999},
url = {https://doi.org/10.1145/309847.310052},
doi = {10.1145/309847.310052},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/PomeranzR99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/LinPR99,
author = {Xijiang Lin and
Irith Pomeranz and
Sudhakar M. Reddy},
title = {Full Scan Fault Coverage With Partial Scan},
booktitle = {1999 Design, Automation and Test in Europe {(DATE} '99), 9-12 March
1999, Munich, Germany},
pages = {468--472},
publisher = {{IEEE} Computer Society / {ACM}},
year = {1999},
url = {https://doi.org/10.1109/DATE.1999.761167},
doi = {10.1109/DATE.1999.761167},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/LinPR99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ets/PomeranzR99,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On avoiding undetectable faults during test generation},
booktitle = {4th European Test Workshop, {ETW} 1999, Constance, Germany, May 25-28,
1999},
pages = {90--95},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/ETW.1999.804292},
doi = {10.1109/ETW.1999.804292},
timestamp = {Tue, 28 Apr 2020 13:37:50 +0200},
biburl = {https://dblp.org/rec/conf/ets/PomeranzR99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/PomeranzR99,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {{PASTA:} Partial Scan to Enhance Test Compaction},
booktitle = {9th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '99), 4-6 March 1999,
Ann Arbor, MI, {USA}},
pages = {4--7},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/GLSV.1999.757364},
doi = {10.1109/GLSV.1999.757364},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/PomeranzR99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/LinPR99,
author = {Xijiang Lin and
Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Jacob K. White and
Ellen Sentovich},
title = {Techniques for improving the efficiency of sequential circuit test
generation},
booktitle = {Proceedings of the 1999 {IEEE/ACM} International Conference on Computer-Aided
Design, 1999, San Jose, California, USA, November 7-11, 1999},
pages = {147--151},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/ICCAD.1999.810639},
doi = {10.1109/ICCAD.1999.810639},
timestamp = {Mon, 08 May 2023 21:43:38 +0200},
biburl = {https://dblp.org/rec/conf/iccad/LinPR99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/PomeranzR99,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Jacob K. White and
Ellen Sentovich},
title = {An approach for improving the levels of compaction achieved by vector
omission},
booktitle = {Proceedings of the 1999 {IEEE/ACM} International Conference on Computer-Aided
Design, 1999, San Jose, California, USA, November 7-11, 1999},
pages = {463--466},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/ICCAD.1999.810694},
doi = {10.1109/ICCAD.1999.810694},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/PomeranzR99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/PomeranzR99,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Fault Simulation Based Test Generation for Combinational Circuits
Using Dynamically Selected Sub-Circuits},
booktitle = {Proceedings of the {IEEE} International Conference On Computer Design,
{VLSI} in Computers and Processors, {ICCD} '99, Austin, Texas, USA,
October 10-13, 1999},
pages = {412--417},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/ICCD.1999.808575},
doi = {10.1109/ICCD.1999.808575},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/PomeranzR99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/PomeranzR99,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On achieving complete coverage of delay faults in full scan circuits
using locally available lines},
booktitle = {Proceedings {IEEE} International Test Conference 1999, Atlantic City,
NJ, USA, 27-30 September 1999},
pages = {923--931},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/TEST.1999.805824},
doi = {10.1109/TEST.1999.805824},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/PomeranzR99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/ShaoGRP99,
author = {Yun Shao and
Ruifeng Guo and
Sudhakar M. Reddy and
Irith Pomeranz},
title = {The effects of test compaction on fault diagnosis},
booktitle = {Proceedings {IEEE} International Test Conference 1999, Atlantic City,
NJ, USA, 27-30 September 1999},
pages = {1083--1089},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/TEST.1999.805842},
doi = {10.1109/TEST.1999.805842},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/ShaoGRP99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/PomeranzR99,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {{VERSE:} {A} Vector Replacement Procedure for Improving Test Compaction
in Synchronous Sequential Circuits},
booktitle = {12th International Conference on {VLSI} Design {(VLSI} Design 1999),
10-13 January 1999, Goa, India},
pages = {250--255},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/ICVD.1999.745156},
doi = {10.1109/ICVD.1999.745156},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/PomeranzR99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/PomeranzZ99,
author = {Irith Pomeranz and
Yervant Zorian},
title = {Testing of Non-Isolated Embedded Legacy Cores and their Surrounding
Logic},
booktitle = {17th {IEEE} {VLSI} Test Symposium {(VTS} '99), 25-30 April 1999, San
Diego, CA, {USA}},
pages = {41--48},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/VTEST.1999.766645},
doi = {10.1109/VTEST.1999.766645},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/PomeranzZ99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/PomeranzR99,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {A Flexible Path Selection Procedure for Path Delay Fault Testing},
booktitle = {17th {IEEE} {VLSI} Test Symposium {(VTS} '99), 25-30 April 1999, San
Diego, CA, {USA}},
pages = {152--159},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/VTEST.1999.766659},
doi = {10.1109/VTEST.1999.766659},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/PomeranzR99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/PomeranzR99a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On n-Detection Test Sets and Variable n-Detection Test Sets for Transition
Faults},
booktitle = {17th {IEEE} {VLSI} Test Symposium {(VTS} '99), 25-30 April 1999, San
Diego, CA, {USA}},
pages = {173--181},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/VTEST.1999.766662},
doi = {10.1109/VTEST.1999.766662},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/PomeranzR99a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/AmyeenFPB99,
author = {M. Enamul Amyeen and
W. Kent Fuchs and
Irith Pomeranz and
Vamsi Boppana},
title = {Implication and Evaluation Techniques for Proving Fault Equivalence},
booktitle = {17th {IEEE} {VLSI} Test Symposium {(VTS} '99), 25-30 April 1999, San
Diego, CA, {USA}},
pages = {201--213},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/VTEST.1999.766666},
doi = {10.1109/VTEST.1999.766666},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/AmyeenFPB99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/GuoPR99,
author = {Ruifeng Guo and
Irith Pomeranz and
Sudhakar M. Reddy},
title = {A Fault Simulation Based Test Pattern Generator for Synchronous Sequential
Circuits},
booktitle = {17th {IEEE} {VLSI} Test Symposium {(VTS} '99), 25-30 April 1999, San
Diego, CA, {USA}},
pages = {260--267},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/VTEST.1999.766674},
doi = {10.1109/VTEST.1999.766674},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/GuoPR99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/ReddyPBL99,
author = {Sudhakar M. Reddy and
Irith Pomeranz and
Nadir Z. Basturkmen and
Xijiang Lin},
title = {Procedures for Identifying Undetectable and Redundant Faults In Synchronous
Sequential Circuits},
booktitle = {17th {IEEE} {VLSI} Test Symposium {(VTS} '99), 25-30 April 1999, San
Diego, CA, {USA}},
pages = {275--283},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/VTEST.1999.766676},
doi = {10.1109/VTEST.1999.766676},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/ReddyPBL99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/PomeranzR98,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Delay fault models for {VLSI} circuits1},
journal = {Integr.},
volume = {26},
number = {1-2},
pages = {21--40},
year = {1998},
url = {https://doi.org/10.1016/S0167-9260(98)00019-4},
doi = {10.1016/S0167-9260(98)00019-4},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/PomeranzR98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/PomeranzR98,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Location of Stuck-At Faults and Bridging Faults Based on Circuit Partitioning},
journal = {{IEEE} Trans. Computers},
volume = {47},
number = {10},
pages = {1124--1135},
year = {1998},
url = {https://doi.org/10.1109/12.729795},
doi = {10.1109/12.729795},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/PomeranzR98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR98,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Low-complexity fault simulation under the multiple observation time
and the restricted multiple observation time testing approaches},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {3},
pages = {269--278},
year = {1998},
url = {https://doi.org/10.1109/43.700724},
doi = {10.1109/43.700724},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR98a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Design-for-testability for path delay faults in large combinational
circuits using test points},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {4},
pages = {333--343},
year = {1998},
url = {https://doi.org/10.1109/43.703823},
doi = {10.1109/43.703823},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR98a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR98b,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Test sequences to achieve high defect coverage for synchronous sequential
circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {10},
pages = {1017--1029},
year = {1998},
url = {https://doi.org/10.1109/43.728921},
doi = {10.1109/43.728921},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR98b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DabholkarCPR98,
author = {Vinay Dabholkar and
Sreejit Chakravarty and
Irith Pomeranz and
Sudhakar M. Reddy},
title = {Techniques for minimizing power dissipation in scan and combinational
circuits during test application},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {12},
pages = {1325--1333},
year = {1998},
url = {https://doi.org/10.1109/43.736572},
doi = {10.1109/43.736572},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DabholkarCPR98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/PomeranzR98,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Functional test generation for delay faults in combinational circuits},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {3},
number = {2},
pages = {231--248},
year = {1998},
url = {https://doi.org/10.1145/290833.290845},
doi = {10.1145/290833.290845},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/PomeranzR98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PomeranzR98,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On methods to match a test pattern generator to a circuit-under-test},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {6},
number = {3},
pages = {432--444},
year = {1998},
url = {https://doi.org/10.1109/92.711314},
doi = {10.1109/92.711314},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PomeranzR98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/PomeranzR98,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Static Test Compaction for Scan-Based Designs to Reduce Test Application
Time},
booktitle = {7th Asian Test Symposium {(ATS} '98), 2-4 December 1998, Singapore},
pages = {198--203},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/ATS.1998.741614},
doi = {10.1109/ATS.1998.741614},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/PomeranzR98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/PomeranzR98a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Test Generation for Synchronous Sequential Circuits to Reduce Storage
Requirements},
booktitle = {7th Asian Test Symposium {(ATS} '98), 2-4 December 1998, Singapore},
pages = {446--451},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/ATS.1998.741655},
doi = {10.1109/ATS.1998.741655},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/PomeranzR98a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/GuoPR98,
author = {Ruifeng Guo and
Irith Pomeranz and
Sudhakar M. Reddy},
title = {On Speeding-Up Vector Restoration Based Static Compaction of Test
Sequences for Sequential Circuits},
booktitle = {7th Asian Test Symposium {(ATS} '98), 2-4 December 1998, Singapore},
pages = {467--471},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/ATS.1998.741658},
doi = {10.1109/ATS.1998.741658},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/GuoPR98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/PomeranzF98,
author = {Irith Pomeranz and
W. Kent Fuchs},
title = {A Diagnostic Test Generation Procedure for Combinational Circuits
Based on Test Elimination},
booktitle = {7th Asian Test Symposium {(ATS} '98), 2-4 December 1998, Singapore},
pages = {486--491},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/ATS.1998.741661},
doi = {10.1109/ATS.1998.741661},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/PomeranzF98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/GuoPR98,
author = {Ruifeng Guo and
Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Patrick M. Dewilde and
Franz J. Rammig and
Gerry Musgrave},
title = {Procedures for Static Compaction of Test Sequences for Synchronous
Sequential Circuits Based on Vector Restoration},
booktitle = {1998 Design, Automation and Test in Europe {(DATE} '98), February
23-26, 1998, Le Palais des Congr{\`{e}}s de Paris, Paris, France},
pages = {583--587},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/DATE.1998.655917},
doi = {10.1109/DATE.1998.655917},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/GuoPR98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PomeranzR98,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Patrick M. Dewilde and
Franz J. Rammig and
Gerry Musgrave},
title = {A Synthesis Procedure for Flexible Logic Functions},
booktitle = {1998 Design, Automation and Test in Europe {(DATE} '98), February
23-26, 1998, Le Palais des Congr{\`{e}}s de Paris, Paris, France},
pages = {973--974},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/DATE.1998.655995},
doi = {10.1109/DATE.1998.655995},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/PomeranzR98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PomeranzR98a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Patrick M. Dewilde and
Franz J. Rammig and
Gerry Musgrave},
title = {Design-for-Testability for Synchronous Sequential Circuits using Locally
Available Lines},
booktitle = {1998 Design, Automation and Test in Europe {(DATE} '98), February
23-26, 1998, Le Palais des Congr{\`{e}}s de Paris, Paris, France},
pages = {983--984},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/DATE.1998.656000},
doi = {10.1109/DATE.1998.656000},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/PomeranzR98a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ftcs/PomeranzR98,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {A Generalized Test Generation Procedure for Path Delay Faults},
booktitle = {Digest of Papers: FTCS-28, The Twenty-Eigth Annual International Symposium
on Fault-Tolerant Computing, Munich, Germany, June 23-25, 1998},
pages = {274--283},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/FTCS.1998.689478},
doi = {10.1109/FTCS.1998.689478},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ftcs/PomeranzR98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/PomeranzR98,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Test Compaction for Synchronous Sequential Circuits by Test Sequence
Recycling},
booktitle = {8th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '98), 19-21 February
1998, Lafayette, LA, {USA}},
pages = {216--221},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/GLSV.1998.665229},
doi = {10.1109/GLSV.1998.665229},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/PomeranzR98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/PomeranzR98,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Improved built-in test pattern generators based on comparison units
for synchronous sequential circuits},
booktitle = {International Conference on Computer Design: {VLSI} in Computers and
Processors, {ICCD} 1998, Proceedings, 5-7 October, 1998, Austin, TX,
{USA}},
pages = {26--31},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/ICCD.1998.727019},
doi = {10.1109/ICCD.1998.727019},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/PomeranzR98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/LinPR98,
author = {Xijiang Lin and
Irith Pomeranz and
Sudhakar M. Reddy},
title = {On finding undetectable and redundant faults in synchronous sequential
circuits},
booktitle = {International Conference on Computer Design: {VLSI} in Computers and
Processors, {ICCD} 1998, Proceedings, 5-7 October, 1998, Austin, TX,
{USA}},
pages = {498--503},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/ICCD.1998.727095},
doi = {10.1109/ICCD.1998.727095},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/LinPR98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/PomeranzR98,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {A diagnostic test generation procedure for synchronous sequential
circuits based on test elimination},
booktitle = {Proceedings {IEEE} International Test Conference 1998, Washington,
DC, USA, October 18-22, 1998},
pages = {1074--1083},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/TEST.1998.743306},
doi = {10.1109/TEST.1998.743306},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/PomeranzR98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/PomeranzR98,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On Test Compaction Objectives for Combinational and Sequential Circuits},
booktitle = {11th International Conference on {VLSI} Design {(VLSI} Design 1991),
4-7 January 1998, Chennai, India},
pages = {279--284},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/ICVD.1998.646618},
doi = {10.1109/ICVD.1998.646618},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/PomeranzR98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/LinPR98,
author = {Xijiang Lin and
Irith Pomeranz and
Sudhakar M. Reddy},
title = {{MIX:} {A} Test Generation System for Synchronous Sequential Circuits},
booktitle = {11th International Conference on {VLSI} Design {(VLSI} Design 1991),
4-7 January 1998, Chennai, India},
pages = {456--463},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/ICVD.1998.646649},
doi = {10.1109/ICVD.1998.646649},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/LinPR98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/PomeranzR98,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On Synchronizing Sequences and Test Sequence Partitioning},
booktitle = {16th {IEEE} {VLSI} Test Symposium {(VTS} '98), 28 April - 1 May 1998,
Princeton, NJ, {USA}},
pages = {158--167},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/VTEST.1998.670864},
doi = {10.1109/VTEST.1998.670864},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/PomeranzR98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/LinPR98,
author = {Xijiang Lin and
Irith Pomeranz and
Sudhakar M. Reddy},
title = {On Removing Redundant Faults in Synchronous Sequential Circuits},
booktitle = {16th {IEEE} {VLSI} Test Symposium {(VTS} '98), 28 April - 1 May 1998,
Princeton, NJ, {USA}},
pages = {168--175},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/VTEST.1998.670865},
doi = {10.1109/VTEST.1998.670865},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/LinPR98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/PomeranzR98a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Stuck-At Tuple-Detection: {A} Fault Model Based on Stuck-At Faults
for Improved Defect Coverage},
booktitle = {16th {IEEE} {VLSI} Test Symposium {(VTS} '98), 28 April - 1 May 1998,
Princeton, NJ, {USA}},
pages = {289--295},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/VTEST.1998.670882},
doi = {10.1109/VTEST.1998.670882},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/PomeranzR98a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/PomeranzR97,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On Dictionary-Based Fault Location in Digital Logic Circuits},
journal = {{IEEE} Trans. Computers},
volume = {46},
number = {1},
pages = {48--59},
year = {1997},
url = {https://doi.org/10.1109/12.559802},
doi = {10.1109/12.559802},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/PomeranzR97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/PomeranzR97a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Test Generation for Multiple State-Table Faults in Finite-State Machines},
journal = {{IEEE} Trans. Computers},
volume = {46},
number = {7},
pages = {783--794},
year = {1997},
url = {https://doi.org/10.1109/12.599899},
doi = {10.1109/12.599899},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/PomeranzR97a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR97,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {{LOCSTEP:} a logic-simulation-based test generation procedure},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {16},
number = {5},
pages = {544--554},
year = {1997},
url = {https://doi.org/10.1109/43.631218},
doi = {10.1109/43.631218},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ReddyPK97,
author = {Sudhakar M. Reddy and
Irith Pomeranz and
Seiji Kajihara},
title = {Compact test sets for high defect coverage},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {16},
number = {8},
pages = {923--930},
year = {1997},
url = {https://doi.org/10.1109/43.644620},
doi = {10.1109/43.644620},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ReddyPK97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR97a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On error correction in macro-based circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {16},
number = {10},
pages = {1088--1100},
year = {1997},
url = {https://doi.org/10.1109/43.662673},
doi = {10.1109/43.662673},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR97a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/PomeranzR97,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On the Compaction of Test Sets Produced by Genetic Optimization},
booktitle = {6th Asian Test Symposium {(ATS} '97), 17-18 November 1997, Akita,
Japan},
pages = {4--9},
publisher = {{IEEE} Computer Society},
year = {1997},
url = {https://doi.org/10.1109/ATS.1997.643906},
doi = {10.1109/ATS.1997.643906},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/PomeranzR97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/PomeranzR97a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {{TEMPLATES:} {A} Test Generation Procedure for Synchronous Sequential
Circuits},
booktitle = {6th Asian Test Symposium {(ATS} '97), 17-18 November 1997, Akita,
Japan},
pages = {74},
publisher = {{IEEE} Computer Society},
year = {1997},
url = {https://doi.org/10.1109/ATS.1997.643923},
doi = {10.1109/ATS.1997.643923},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/PomeranzR97a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/PomeranzR97,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Ellen J. Yoffa and
Giovanni De Micheli and
Jan M. Rabaey},
title = {Fault Simulation under the Multiple Observation Time Approach using
Backward Implications},
booktitle = {Proceedings of the 34st Conference on Design Automation, Anaheim,
California, USA, Anaheim Convention Center, June 9-13, 1997},
pages = {608--613},
publisher = {{ACM} Press},
year = {1997},
url = {https://doi.org/10.1145/266021.266297},
doi = {10.1145/266021.266297},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/PomeranzR97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PomeranzR97,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On improving genetic optimization based test generation},
booktitle = {European Design and Test Conference, ED{\&}TC '97, Paris, France,
17-20 March 1997},
pages = {506--511},
publisher = {{IEEE} Computer Society},
year = {1997},
url = {https://doi.org/10.1109/EDTC.1997.582408},
doi = {10.1109/EDTC.1997.582408},
timestamp = {Fri, 20 May 2022 15:59:03 +0200},
biburl = {https://dblp.org/rec/conf/date/PomeranzR97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PomeranzR97a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On the use of reset to increase the testability of interconnected
finite-state machines},
booktitle = {European Design and Test Conference, ED{\&}TC '97, Paris, France,
17-20 March 1997},
pages = {554--559},
publisher = {{IEEE} Computer Society},
year = {1997},
url = {https://doi.org/10.1109/EDTC.1997.582416},
doi = {10.1109/EDTC.1997.582416},
timestamp = {Tue, 28 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/PomeranzR97a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ftcs/PomeranzR97,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {{ACTIV-LOCSTEP:} {A} Test Generation Procedure Based on Logic Simulation
and Fault Activation},
booktitle = {Digest of Papers: FTCS-27, The Twenty-Seventh Annual International
Symposium on Fault-Tolerant Computing, Seattle, Washington, USA, June
24-27, 1997},
pages = {144--151},
publisher = {{IEEE} Computer Society},
year = {1997},
url = {https://doi.org/10.1109/FTCS.1997.614087},
doi = {10.1109/FTCS.1997.614087},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ftcs/PomeranzR97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/PomeranzR97,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On Generating Test Sets that Remain Valid in the Presence of Undetected
Faults},
booktitle = {7th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '97), 13-15 March
1997, Urbana, IL, {USA}},
pages = {20--25},
publisher = {{IEEE} Computer Society},
year = {1997},
url = {https://doi.org/10.1109/GLSV.1997.580405},
doi = {10.1109/GLSV.1997.580405},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/PomeranzR97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/PomeranzR97,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Ralph H. J. M. Otten and
Hiroto Yasuura},
title = {Built-in test generation for synchronous sequential circuits},
booktitle = {Proceedings of the 1997 {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 1997, San Jose, CA, USA, November 9-13, 1997},
pages = {421--426},
publisher = {{IEEE} Computer Society / {ACM}},
year = {1997},
url = {https://doi.org/10.1109/ICCAD.1997.643570},
doi = {10.1109/ICCAD.1997.643570},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/PomeranzR97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/PomeranzR97,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Vector Restoration Based Static Compaction of Test Sequences for Synchronous
Sequential Circuits},
booktitle = {Proceedings 1997 International Conference on Computer Design: {VLSI}
in Computers {\&} Processors, {ICCD} '97, Austin, Texas, USA,
October 12-15, 1997},
pages = {360--365},
publisher = {{IEEE} Computer Society},
year = {1997},
url = {https://doi.org/10.1109/ICCD.1997.628895},
doi = {10.1109/ICCD.1997.628895},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/PomeranzR97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/KajiharaKPR97,
author = {Seiji Kajihara and
Kozo Kinoshita and
Irith Pomeranz and
Sudhakar M. Reddy},
title = {A Method for Identifying Robust Dependent and Functionally Unsensitizable
Paths},
booktitle = {10th International Conference on {VLSI} Design {(VLSI} Design 1997),
4-7 January 1997, Hyderabad, India},
pages = {82--87},
publisher = {{IEEE} Computer Society},
year = {1997},
url = {https://doi.org/10.1109/ICVD.1997.567965},
doi = {10.1109/ICVD.1997.567965},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/KajiharaKPR97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/PomeranzR97,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On the Detection of Reset Faults in Synchronous Sequential Circuits},
booktitle = {10th International Conference on {VLSI} Design {(VLSI} Design 1997),
4-7 January 1997, Hyderabad, India},
pages = {470--474},
publisher = {{IEEE} Computer Society},
year = {1997},
url = {https://doi.org/10.1109/ICVD.1997.568179},
doi = {10.1109/ICVD.1997.568179},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/PomeranzR97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/PomeranzR97a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On Full Reset as a Design-For-Testability Technique},
booktitle = {10th International Conference on {VLSI} Design {(VLSI} Design 1997),
4-7 January 1997, Hyderabad, India},
pages = {534--536},
publisher = {{IEEE} Computer Society},
year = {1997},
url = {https://doi.org/10.1109/ICVD.1997.568201},
doi = {10.1109/ICVD.1997.568201},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/PomeranzR97a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/PomeranzR97,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {{EXTEST:} a method to extend test sequences of synchronous sequential
circuits to increase the fault coverage},
booktitle = {15th {IEEE} {VLSI} Test Symposium (VTS'97), April 27-May 1, 1997,
Monterey, California, {USA}},
pages = {329--335},
publisher = {{IEEE} Computer Society},
year = {1997},
url = {https://doi.org/10.1109/VTEST.1997.600297},
doi = {10.1109/VTEST.1997.600297},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/PomeranzR97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/PomeranzR97a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On n-detection test sequences for synchronous sequential circuits343},
booktitle = {15th {IEEE} {VLSI} Test Symposium (VTS'97), April 27-May 1, 1997,
Monterey, California, {USA}},
pages = {336--343},
publisher = {{IEEE} Computer Society},
year = {1997},
url = {https://doi.org/10.1109/VTEST.1997.600299},
doi = {10.1109/VTEST.1997.600299},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/PomeranzR97a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/PomeranzR96,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On Removing Redundancies from Synchronous Sequential Circuits with
Synchronizing Sequences},
journal = {{IEEE} Trans. Computers},
volume = {45},
number = {1},
pages = {20--32},
year = {1996},
url = {https://doi.org/10.1109/12.481483},
doi = {10.1109/12.481483},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/PomeranzR96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/PomeranzR96a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On the Number of Tests to Detect All Path Delay Faults in Combinational
Logic Circuits},
journal = {{IEEE} Trans. Computers},
volume = {45},
number = {1},
pages = {50--62},
year = {1996},
url = {https://doi.org/10.1109/12.481486},
doi = {10.1109/12.481486},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/PomeranzR96a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/PomeranzR96,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On Test Generation for Interconnected Finite-State Machines: The Input
Sequence Propagation Problem},
booktitle = {5th Asian Test Symposium {(ATS} '96), November 20-22, 1996, Hsinchu,
Taiwan},
pages = {16--21},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/ATS.1996.555129},
doi = {10.1109/ATS.1996.555129},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/PomeranzR96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/PomeranzR96a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Low-Complexity Fault Diagnosis Under the Multiple Observation Time
Testing Approach},
booktitle = {5th Asian Test Symposium {(ATS} '96), November 20-22, 1996, Hsinchu,
Taiwan},
pages = {226--231},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/ATS.1996.555163},
doi = {10.1109/ATS.1996.555163},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/PomeranzR96a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/PomeranzR96,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Thomas Pennino and
Ellen J. Yoffa},
title = {On Static Compaction of Test Sequences for Synchronous Sequential
Circuits},
booktitle = {Proceedings of the 33st Conference on Design Automation, Las Vegas,
Nevada, USA, Las Vegas Convention Center, June 3-7, 1996},
pages = {215--220},
publisher = {{ACM} Press},
year = {1996},
url = {https://doi.org/10.1145/240518.240558},
doi = {10.1145/240518.240558},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/PomeranzR96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/PomeranzR96,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On Test Generation for Interconnected Finite-State Machines - The
Output Sequence Justification Problem},
booktitle = {1996 European Design and Test Conference, ED{\&}TC 1996, Paris,
France, March 11-14, 1996},
pages = {380--387},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/EDTC.1996.494329},
doi = {10.1109/EDTC.1996.494329},
timestamp = {Fri, 20 May 2022 15:52:30 +0200},
biburl = {https://dblp.org/rec/conf/date/PomeranzR96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ftcs/PomeranzR96,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Dynamic Test Compaction for Synchronous Sequential Circuits using
Static Compaction Techniques},
booktitle = {Digest of Papers: FTCS-26, The Twenty-Sixth Annual International Symposium
on Fault-Tolerant Computing, Sendai, Japan, June 25-27, 1996},
pages = {53--61},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/FTCS.1996.534594},
doi = {10.1109/FTCS.1996.534594},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ftcs/PomeranzR96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/PomeranzRP96,
author = {Irith Pomeranz and
Sudhakar M. Reddy and
Janak H. Patel},
title = {On Double Transition Faults as a Delay Fault Model},
booktitle = {6th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '96), March 22-23,
1996, Ames, IA, {USA}},
pages = {282--287},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/GLSV.1996.497634},
doi = {10.1109/GLSV.1996.497634},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/PomeranzRP96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/PomeranzR96a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Fault Location Based on Circuit Partitioning},
booktitle = {1996 International Conference on Computer Design {(ICCD} '96), {VLSI}
in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings},
pages = {242--247},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/ICCD.1996.563563},
doi = {10.1109/ICCD.1996.563563},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/PomeranzR96a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/RudnickPP96,
author = {Elizabeth M. Rudnick and
Janak H. Patel and
Irith Pomeranz},
title = {On Potential Fault Detection in Sequential Circuits},
booktitle = {Proceedings {IEEE} International Test Conference 1996, Test and Design
Validity, Washington, DC, USA, October 20-25, 1996},
pages = {142--149},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/TEST.1996.556956},
doi = {10.1109/TEST.1996.556956},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/RudnickPP96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/PomeranzR96,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On Cancelling the Effects of Logic Sharing for Improved Path Delay
Fault Testability},
booktitle = {Proceedings {IEEE} International Test Conference 1996, Test and Design
Validity, Washington, DC, USA, October 20-25, 1996},
pages = {357--366},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/TEST.1996.556982},
doi = {10.1109/TEST.1996.556982},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/PomeranzR96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/PomeranzSRKL96,
author = {Irith Pomeranz and
Nirmal R. Saxena and
Richard Reeve and
Paritosh Kulkarni and
Yan A. Li},
title = {Generation of Test Cases for Hardware Design Verification of a Super-Scalar
Fetch Processor},
booktitle = {Proceedings {IEEE} International Test Conference 1996, Test and Design
Validity, Washington, DC, USA, October 20-25, 1996},
pages = {904--913},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/TEST.1996.557152},
doi = {10.1109/TEST.1996.557152},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/PomeranzSRKL96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/PomeranzR96,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On Finding Functionally Identical and Functionally Opposite Lines
in Combinational Logic Circuits},
booktitle = {9th International Conference on {VLSI} Design {(VLSI} Design 1996),
3-6 January 1996, Bangalore, India},
pages = {254--259},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/ICVD.1996.489495},
doi = {10.1109/ICVD.1996.489495},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/PomeranzR96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/LuP96,
author = {Yuan Lu and
Irith Pomeranz},
title = {Synchronization of large sequential circuits by partial reset},
booktitle = {14th {IEEE} {VLSI} Test Symposium (VTS'96), April 28 - May 1, 1996,
Princeton, NJ, {USA}},
pages = {93--98},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/VTEST.1996.510841},
doi = {10.1109/VTEST.1996.510841},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/LuP96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/UppaluriSP96,
author = {Prasanti Uppaluri and
Uwe Sparmann and
Irith Pomeranz},
title = {On minimizing the number of test points needed to achieve complete
robust path delay fault testability},
booktitle = {14th {IEEE} {VLSI} Test Symposium (VTS'96), April 28 - May 1, 1996,
Princeton, NJ, {USA}},
pages = {288--295},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/VTEST.1996.510870},
doi = {10.1109/VTEST.1996.510870},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/UppaluriSP96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/ReddyPK96,
author = {Sudhakar M. Reddy and
Irith Pomeranz and
Seiji Kajihara},
title = {On the effects of test compaction on defect coverage},
booktitle = {14th {IEEE} {VLSI} Test Symposium (VTS'96), April 28 - May 1, 1996,
Princeton, NJ, {USA}},
pages = {430--437},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/VTEST.1996.510889},
doi = {10.1109/VTEST.1996.510889},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/ReddyPK96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/et/OrensteinKP95,
author = {Tatiana Orenstein and
Zvi Kohavi and
Irith Pomeranz},
title = {An optimal algorithm for cycle breaking in directed graphs},
journal = {J. Electron. Test.},
volume = {7},
number = {1-2},
pages = {71--81},
year = {1995},
url = {https://doi.org/10.1007/BF00993315},
doi = {10.1007/BF00993315},
timestamp = {Fri, 11 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/et/OrensteinKP95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/PomeranzR95,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Aliasing Computation Using Fault Simulation with Fault Dropping},
journal = {{IEEE} Trans. Computers},
volume = {44},
number = {1},
pages = {139--144},
year = {1995},
url = {https://doi.org/10.1109/12.368001},
doi = {10.1109/12.368001},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/PomeranzR95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/PomeranzR95a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On Fault Simulation for Synchronous Sequential Circuits},
journal = {{IEEE} Trans. Computers},
volume = {44},
number = {2},
pages = {335--340},
year = {1995},
url = {https://doi.org/10.1109/12.364543},
doi = {10.1109/12.364543},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/PomeranzR95a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/PomeranzR95b,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {{INCREDYBLE:} {A} New Search Strategy for Design Automation Problems
with Applications to Testing},
journal = {{IEEE} Trans. Computers},
volume = {44},
number = {6},
pages = {792--804},
year = {1995},
url = {https://doi.org/10.1109/12.391182},
doi = {10.1109/12.391182},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/PomeranzR95b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR95,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On correction of multiple design errors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {14},
number = {2},
pages = {255--264},
year = {1995},
url = {https://doi.org/10.1109/43.370421},
doi = {10.1109/43.370421},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KajiharaPKR95,
author = {Seiji Kajihara and
Irith Pomeranz and
Kozo Kinoshita and
Sudhakar M. Reddy},
title = {Cost-effective generation of minimal test sets for stuck-at faults
in combinational logic circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {14},
number = {12},
pages = {1496--1504},
year = {1995},
url = {https://doi.org/10.1109/43.476580},
doi = {10.1109/43.476580},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KajiharaPKR95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzRU95,
author = {Irith Pomeranz and
Sudhakar M. Reddy and
Prasanti Uppaluri},
title = {{NEST:} a nonenumerative test generation method for path delay faults
in combinational circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {14},
number = {12},
pages = {1505--1515},
year = {1995},
url = {https://doi.org/10.1109/43.476581},
doi = {10.1109/43.476581},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzRU95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/PomeranzR95,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Static compaction for two-pattern test sets},
booktitle = {4th Asian Test Symposium {(ATS} '95), November 23-24, 1995. Bangalore,
India},
pages = {222--228},
publisher = {{IEEE} Computer Society},
year = {1995},
url = {https://doi.org/10.1109/ATS.1995.485340},
doi = {10.1109/ATS.1995.485340},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/PomeranzR95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/PomeranzR95,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Bryan Preas},
title = {On Synthesis-for-Testability of Combinational Logic Circuits},
booktitle = {Proceedings of the 32st Conference on Design Automation, San Francisco,
California, USA, Moscone Center, June 12-16, 1995},
pages = {126--132},
publisher = {{ACM} Press},
year = {1995},
url = {https://doi.org/10.1145/217474.217518},
doi = {10.1145/217474.217518},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/PomeranzR95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/eurodac/PomeranzR95,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Gerald Musgrave},
title = {On generating compact test sequences for synchronous sequential circuits},
booktitle = {Proceedings EURO-DAC'95, European Design Automation Conference with
EURO-VHDL, Brighton, England, UK, September 18-22, 1995},
pages = {105--110},
publisher = {{IEEE} Computer Society},
year = {1995},
url = {https://doi.org/10.1109/EURDAC.1995.527394},
doi = {10.1109/EURDAC.1995.527394},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/eurodac/PomeranzR95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ftcs/PomeranzR95,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {{LOCSTEP:} {A} Logic Simulation Based Test Generation Procedure},
booktitle = {Digest of Papers: FTCS-25, The Twenty-Fifth International Symposium
on Fault-Tolerant Computing, Pasadena, California, USA, June 27-30,
1995},
pages = {110--119},
publisher = {{IEEE} Computer Society},
year = {1995},
url = {https://doi.org/10.1109/FTCS.1995.466992},
doi = {10.1109/FTCS.1995.466992},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ftcs/PomeranzR95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/PomeranzR95,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Richard L. Rudell},
title = {Functional test generation for delay faults in combinational circuits},
booktitle = {Proceedings of the 1995 {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 1995, San Jose, California, USA, November 5-9, 1995},
pages = {687--694},
publisher = {{IEEE} Computer Society / {ACM}},
year = {1995},
url = {https://doi.org/10.1109/ICCAD.1995.480204},
doi = {10.1109/ICCAD.1995.480204},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/PomeranzR95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/PomeranzR95,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Test generation for multiple state-table faults in finite-state machines},
booktitle = {1995 International Conference on Computer Design {(ICCD} '95), {VLSI}
in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings},
pages = {292--297},
publisher = {{IEEE} Computer Society},
year = {1995},
url = {https://doi.org/10.1109/ICCD.1995.528824},
doi = {10.1109/ICCD.1995.528824},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/PomeranzR95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/PomeranzR95,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Low-Complexity Fault Simulation under the Multiplie Observation Time
Testing Approach},
booktitle = {Proceedings {IEEE} International Test Conference 1995, Driving Down
the Cost of Test, Washington, DC, USA, October 21-25, 1995},
pages = {272--281},
publisher = {{IEEE} Computer Society},
year = {1995},
url = {https://doi.org/10.1109/TEST.1995.529842},
doi = {10.1109/TEST.1995.529842},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/PomeranzR95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/YadavalliPR95,
author = {Sitaran Yadavalli and
Irith Pomeranz and
Sudhakar M. Reddy},
title = {MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer
Level},
booktitle = {8th International Conference on {VLSI} Design {(VLSI} Design 1995),
4-7 January 1995, New Delhi, India},
pages = {110--115},
publisher = {{IEEE} Computer Society},
year = {1995},
url = {https://doi.org/10.1109/ICVD.1995.512087},
doi = {10.1109/ICVD.1995.512087},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/YadavalliPR95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/ReddyPRK95,
author = {Remata S. Reddy and
Irith Pomeranz and
Sudhakar M. Reddy and
Seiji Kajihara},
title = {Compact test generation for bridging faults under I\({}_{\mbox{DDQ}}\)
testing},
booktitle = {13th {IEEE} {VLSI} Test Symposium (VTS'95), April 30 - May 3, 1995,
Princeton, New Jersey, {USA}},
pages = {310--316},
publisher = {{IEEE} Computer Society},
year = {1995},
url = {https://doi.org/10.1109/VTEST.1995.512654},
doi = {10.1109/VTEST.1995.512654},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/ReddyPRK95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/PomeranzR94,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Application of Homing Sequences to Synchronous Sequential Circuit
Testing},
journal = {{IEEE} Trans. Computers},
volume = {43},
number = {5},
pages = {569--580},
year = {1994},
url = {https://doi.org/10.1109/12.280804},
doi = {10.1109/12.280804},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/PomeranzR94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/PomeranzR94a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On the Role of Hardware Reset in Synchronous Sequential Circuit Test
Generation},
journal = {{IEEE} Trans. Computers},
volume = {43},
number = {9},
pages = {1100--1105},
year = {1994},
url = {https://doi.org/10.1109/12.312119},
doi = {10.1109/12.312119},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/PomeranzR94a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR94,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {An efficient nonenumerative method to estimate the path delay fault
coverage in combinational circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {13},
number = {2},
pages = {240--250},
year = {1994},
url = {https://doi.org/10.1109/43.259947},
doi = {10.1109/43.259947},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR94a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {{SPADES-ACE:} a simulator for path delay faults in sequential circuits
with extensions to arbitrary clocking schemes},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {13},
number = {2},
pages = {251--263},
year = {1994},
url = {https://doi.org/10.1109/43.259948},
doi = {10.1109/43.259948},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR94a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR94b,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On achieving complete fault coverage for sequential machines},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {13},
number = {3},
pages = {378--386},
year = {1994},
url = {https://doi.org/10.1109/43.265679},
doi = {10.1109/43.265679},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR94b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR94c,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On determining symmetries in inputs of logic circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {13},
number = {11},
pages = {1428--1434},
year = {1994},
url = {https://doi.org/10.1109/43.329273},
doi = {10.1109/43.329273},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR94c.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/PomeranzR94,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Michael J. Lorenzetti},
title = {Design-for-Testability for Path Delay Faults in Large Combinatorial
Circuits Using Test-Points},
booktitle = {Proceedings of the 31st Conference on Design Automation, San Diego,
California, USA, June 6-10, 1994},
pages = {358--364},
publisher = {{ACM} Press},
year = {1994},
url = {https://doi.org/10.1145/196244.196421},
doi = {10.1145/196244.196421},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/PomeranzR94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/PomeranzR94a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Michael J. Lorenzetti},
title = {On Improving Fault Diagnosis for Synchronous Sequential Circuits},
booktitle = {Proceedings of the 31st Conference on Design Automation, San Diego,
California, USA, June 6-10, 1994},
pages = {504--509},
publisher = {{ACM} Press},
year = {1994},
url = {https://doi.org/10.1145/196244.196517},
doi = {10.1145/196244.196517},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/PomeranzR94a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ftcs/ReddyPJ94,
author = {Sudhakar M. Reddy and
Irith Pomeranz and
Rahul Jain},
title = {On Codeword Testing of Two-Rail and Parity {TSC} Checkers},
booktitle = {Digest of Papers: FTCS/24, The Twenty-Fourth Annual International
Symposium on Fault-Tolerant Computing, Austin, Texas, USA, June 15-17,
1994},
pages = {116--125},
publisher = {{IEEE} Computer Society},
year = {1994},
url = {https://doi.org/10.1109/FTCS.1994.315651},
doi = {10.1109/FTCS.1994.315651},
timestamp = {Wed, 16 Oct 2019 14:14:57 +0200},
biburl = {https://dblp.org/rec/conf/ftcs/ReddyPJ94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ftcs/UppaluriPR94,
author = {Prasanti Uppaluri and
Irith Pomeranz and
Sudhakar M. Reddy},
title = {Test Pattern Generation for Path Delay Faults in Synchronous Sequential
Circuits Using Multiple Fast Clocks and Multiple Observations Times},
booktitle = {Digest of Papers: FTCS/24, The Twenty-Fourth Annual International
Symposium on Fault-Tolerant Computing, Austin, Texas, USA, June 15-17,
1994},
pages = {456--465},
publisher = {{IEEE} Computer Society},
year = {1994},
url = {https://doi.org/10.1109/FTCS.1994.315617},
doi = {10.1109/FTCS.1994.315617},
timestamp = {Tue, 23 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ftcs/UppaluriPR94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/PomeranzR94,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Jochen A. G. Jess and
Richard L. Rudell},
title = {On testing delay faults in macro-based combinational circuits},
booktitle = {Proceedings of the 1994 {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 1994, San Jose, California, USA, November 6-10, 1994},
pages = {332--339},
publisher = {{IEEE} Computer Society / {ACM}},
year = {1994},
url = {https://doi.org/10.1109/ICCAD.1994.629813},
doi = {10.1109/ICCAD.1994.629813},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/PomeranzR94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/PomeranzR94a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Jochen A. G. Jess and
Richard L. Rudell},
title = {On error correction in macro-based circuits},
booktitle = {Proceedings of the 1994 {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 1994, San Jose, California, USA, November 6-10, 1994},
pages = {568--575},
publisher = {{IEEE} Computer Society / {ACM}},
year = {1994},
url = {https://doi.org/10.1109/ICCAD.1994.629877},
doi = {10.1109/ICCAD.1994.629877},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/PomeranzR94a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/PomeranzR94,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On Achieving Complete Testability of Synchronous Sequential Circuits
with Synchronizing Sequences},
booktitle = {Proceedings {IEEE} International Test Conference 1994, {TEST:} The
Next 25 Years, Washington, DC, USA, October 2-6, 1994},
pages = {1007--1016},
publisher = {{IEEE} Computer Society},
year = {1994},
url = {https://doi.org/10.1109/TEST.1994.528050},
doi = {10.1109/TEST.1994.528050},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/PomeranzR94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/PomeranzR94,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On Determining Symmetries in Inputs of Logic Circuits},
booktitle = {Proceedings of the Seventh International Conference on {VLSI} Design,
{VLSI} Design 1994, Calcutta, India, January 5-8, 1994},
pages = {255--260},
publisher = {{IEEE} Computer Society},
year = {1994},
url = {https://doi.org/10.1109/ICVD.1994.282697},
doi = {10.1109/ICVD.1994.282697},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/PomeranzR94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/PomeranzR94,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On identifying undetectable and redundant faults in synchronous sequential
circuits},
booktitle = {12th {IEEE} {VLSI} Test Symposium (VTS'94), April 25-28, 1994, Cherry
Hill, New Jersey, {USA}},
pages = {8--14},
publisher = {{IEEE} Computer Society},
year = {1994},
url = {https://doi.org/10.1109/VTEST.1994.292341},
doi = {10.1109/VTEST.1994.292341},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/PomeranzR94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/KajiharaPKR94,
author = {Seiji Kajihara and
Irith Pomeranz and
Kozo Kinoshita and
Sudhakar M. Reddy},
title = {On compacting test sets by addition and removal of test vectors},
booktitle = {12th {IEEE} {VLSI} Test Symposium (VTS'94), April 25-28, 1994, Cherry
Hill, New Jersey, {USA}},
pages = {202--207},
publisher = {{IEEE} Computer Society},
year = {1994},
url = {https://doi.org/10.1109/VTEST.1994.292312},
doi = {10.1109/VTEST.1994.292312},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/KajiharaPKR94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/PomeranzR93,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Classification of Faults in Synchronous Sequential Circuits},
journal = {{IEEE} Trans. Computers},
volume = {42},
number = {9},
pages = {1066--1077},
year = {1993},
url = {https://doi.org/10.1109/12.241596},
doi = {10.1109/12.241596},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/PomeranzR93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/PomeranzR93a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Testing of Fault-Tolerant Hardware Through Partial Control of Inputs},
journal = {{IEEE} Trans. Computers},
volume = {42},
number = {10},
pages = {1267--1271},
year = {1993},
url = {https://doi.org/10.1109/12.257713},
doi = {10.1109/12.257713},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/PomeranzR93a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzRR93,
author = {Irith Pomeranz and
Lakshmi N. Reddy and
Sudhakar M. Reddy},
title = {{COMPACTEST:} a method to generate compact test sets for combinational
circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {12},
number = {7},
pages = {1040--1049},
year = {1993},
url = {https://doi.org/10.1109/43.238040},
doi = {10.1109/43.238040},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzRR93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzR93,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {3-weight pseudo-random test generation based on a deterministic test
set for combinational and sequential circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {12},
number = {7},
pages = {1050--1058},
year = {1993},
url = {https://doi.org/10.1109/43.238041},
doi = {10.1109/43.238041},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzR93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzC93,
author = {Irith Pomeranz and
Kwang{-}Ting Cheng},
title = {{STOIC:} state assignment based on output/input functions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {12},
number = {8},
pages = {1123--1131},
year = {1993},
url = {https://doi.org/10.1109/43.238605},
doi = {10.1109/43.238605},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzC93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/PomeranzR93,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Alfred E. Dunlop},
title = {\emph{INCREDYBLE-TG}: INCREmental DYnamic test generation based on
LEarning},
booktitle = {Proceedings of the 30th Design Automation Conference. Dallas, Texas,
USA, June 14-18, 1993},
pages = {80--85},
publisher = {{ACM} Press},
year = {1993},
url = {https://doi.org/10.1145/157485.164583},
doi = {10.1145/157485.164583},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/PomeranzR93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/KajiharaPKR93,
author = {Seiji Kajihara and
Irith Pomeranz and
Kozo Kinoshita and
Sudhakar M. Reddy},
editor = {Alfred E. Dunlop},
title = {Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults
in Combinational Logic Circuits},
booktitle = {Proceedings of the 30th Design Automation Conference. Dallas, Texas,
USA, June 14-18, 1993},
pages = {102--106},
publisher = {{ACM} Press},
year = {1993},
url = {https://doi.org/10.1145/157485.164617},
doi = {10.1145/157485.164617},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/KajiharaPKR93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/PomeranzRU93,
author = {Irith Pomeranz and
Sudhakar M. Reddy and
Prasanti Uppaluri},
editor = {Alfred E. Dunlop},
title = {{NEST:} {A} Non-Enumerative Test Generation Method for Path Delay
Faults in Combinational Circuits},
booktitle = {Proceedings of the 30th Design Automation Conference. Dallas, Texas,
USA, June 14-18, 1993},
pages = {439--445},
publisher = {{ACM} Press},
year = {1993},
url = {https://doi.org/10.1145/157485.164967},
doi = {10.1145/157485.164967},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/PomeranzRU93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/eurodac/PomeranzR93,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {A method for diagnosing implementation errors in synchronous sequential
circuits and its implications on synthesis},
booktitle = {Proceedings of the European Design Automation Conference 1993, {EURO-DAC}
'93 with EURO-VHDL'93, Hamburg, Germany, September 20-24, 1993},
pages = {252--258},
publisher = {{IEEE} Computer Society},
year = {1993},
url = {https://doi.org/10.1109/EURDAC.1993.410646},
doi = {10.1109/EURDAC.1993.410646},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/eurodac/PomeranzR93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/eurodac/KommuP93,
author = {Venkataramana Kommu and
Irith Pomeranz},
title = {{GAFPGA:} Genetic algorithm for {FPGA} technology mapping},
booktitle = {Proceedings of the European Design Automation Conference 1993, {EURO-DAC}
'93 with EURO-VHDL'93, Hamburg, Germany, September 20-24, 1993},
pages = {300--305},
publisher = {{IEEE} Computer Society},
year = {1993},
url = {https://doi.org/10.1109/EURDAC.1993.410654},
doi = {10.1109/EURDAC.1993.410654},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/eurodac/KommuP93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ftcs/PomeranzR93,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {{EXOP} (Extended Operation): {A} New Logical Fault Model for Digital
Circuits},
booktitle = {Digest of Papers: FTCS-23, The Twenty-Third Annual International Symposium
on Fault-Tolerant Computing, Toulouse, France, June 22-24, 1993},
pages = {166--175},
publisher = {{IEEE} Computer Society},
year = {1993},
url = {https://doi.org/10.1109/FTCS.1993.627320},
doi = {10.1109/FTCS.1993.627320},
timestamp = {Wed, 16 Oct 2019 14:14:57 +0200},
biburl = {https://dblp.org/rec/conf/ftcs/PomeranzR93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ftcs/PomeranzRP93,
author = {Irith Pomeranz and
Sudhakar M. Reddy and
Janak H. Patel},
title = {Theory and Practice of Sequential Machine Testing and Testability},
booktitle = {Digest of Papers: FTCS-23, The Twenty-Third Annual International Symposium
on Fault-Tolerant Computing, Toulouse, France, June 22-24, 1993},
pages = {330--337},
publisher = {{IEEE} Computer Society},
year = {1993},
url = {https://doi.org/10.1109/FTCS.1993.627336},
doi = {10.1109/FTCS.1993.627336},
timestamp = {Tue, 23 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ftcs/PomeranzRP93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ftcs/PomeranzR93a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Design and Synthesis for Testability of Synchronous Sequential Circuits
Based on Strong-Connectivity},
booktitle = {Digest of Papers: FTCS-23, The Twenty-Third Annual International Symposium
on Fault-Tolerant Computing, Toulouse, France, June 22-24, 1993},
pages = {492--501},
publisher = {{IEEE} Computer Society},
year = {1993},
url = {https://doi.org/10.1109/FTCS.1993.627352},
doi = {10.1109/FTCS.1993.627352},
timestamp = {Tue, 23 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ftcs/PomeranzR93a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/PomeranzR93,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Michael R. Lightner and
Jochen A. G. Jess},
title = {Test generation for path delay faults based on learning},
booktitle = {Proceedings of the 1993 {IEEE/ACM} International Conference on Computer-Aided
Design, 1993, Santa Clara, California, USA, November 7-11, 1993},
pages = {428--435},
publisher = {{IEEE} Computer Society / {ACM}},
year = {1993},
url = {https://doi.org/10.1109/ICCAD.1993.580092},
doi = {10.1109/ICCAD.1993.580092},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/PomeranzR93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/PomeranzR93a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Michael R. Lightner and
Jochen A. G. Jess},
title = {On diagnosis and correction of design errors},
booktitle = {Proceedings of the 1993 {IEEE/ACM} International Conference on Computer-Aided
Design, 1993, Santa Clara, California, USA, November 7-11, 1993},
pages = {500--507},
publisher = {{IEEE} Computer Society / {ACM}},
year = {1993},
url = {https://doi.org/10.1109/ICCAD.1993.580104},
doi = {10.1109/ICCAD.1993.580104},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/PomeranzR93a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/RyanFP93,
author = {Paul G. Ryan and
W. Kent Fuchs and
Irith Pomeranz},
editor = {Michael R. Lightner and
Jochen A. G. Jess},
title = {Fault dictionary compression and equivalence class computation for
sequential circuits},
booktitle = {Proceedings of the 1993 {IEEE/ACM} International Conference on Computer-Aided
Design, 1993, Santa Clara, California, USA, November 7-11, 1993},
pages = {508--511},
publisher = {{IEEE} Computer Society / {ACM}},
year = {1993},
url = {https://doi.org/10.1109/ICCAD.1993.580105},
doi = {10.1109/ICCAD.1993.580105},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/RyanFP93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/PomeranzR93,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {A Learning-Based Method to Match a Test Pattern Generator to a Circuit-Under-Test},
booktitle = {Proceedings {IEEE} International Test Conference 1993, Designing,
Testing, and Diagnostics - Join Them, Baltimore, Maryland, USA, October
17-21, 1993},
pages = {998--1007},
publisher = {{IEEE} Computer Society},
year = {1993},
url = {https://doi.org/10.1109/TEST.1993.470599},
doi = {10.1109/TEST.1993.470599},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/PomeranzR93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/PomeranzR93,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {On the Generation of Weights for Weighted Pseudo Random Testing},
booktitle = {Proceedings of the Sixth International Conference on {VLSI} Design,
{VLSI} Design 1993, Bombay, India, January 3-6, 1993},
pages = {69--72},
publisher = {{IEEE} Computer Society},
year = {1993},
url = {https://doi.org/10.1109/ICVD.1993.669641},
doi = {10.1109/ICVD.1993.669641},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/PomeranzR93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/PomeranzR93,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Aliasing computation using fault simulation with fault dropping},
booktitle = {11th {IEEE} {VLSI} Test Symposium (VTS'93), 6 Apr 1993-8 Apr 1993,
Atlantic City, NJ, {USA}},
pages = {282--288},
publisher = {{IEEE} Computer Society},
year = {1993},
url = {https://doi.org/10.1109/VTEST.1993.313358},
doi = {10.1109/VTEST.1993.313358},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/PomeranzR93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/PomeranzR92,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {The Multiple Observation Time Test Strategy},
journal = {{IEEE} Trans. Computers},
volume = {41},
number = {5},
pages = {627--637},
year = {1992},
url = {https://doi.org/10.1109/12.142689},
doi = {10.1109/12.142689},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/PomeranzR92.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PomeranzK92,
author = {Irith Pomeranz and
Zvi Kohavi},
title = {A limited exponential complexity algorithm for increasing the testability
of digital circuits by testing-module insertion},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {11},
number = {2},
pages = {247--259},
year = {1992},
url = {https://doi.org/10.1109/43.124403},
doi = {10.1109/43.124403},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PomeranzK92.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/PomeranzR92,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Daniel G. Schweikert},
title = {At-Speed Delay Testing of Synchronous Sequential Circuits},
booktitle = {Proceedings of the 29th Design Automation Conference, Anaheim, California,
USA, June 8-12, 1992},
pages = {177--181},
publisher = {{IEEE} Computer Society Press},
year = {1992},
url = {http://portal.acm.org/citation.cfm?id=113938.110356},
timestamp = {Thu, 16 Mar 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/PomeranzR92.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/PomeranzC92,
author = {Irith Pomeranz and
Kwang{-}Ting Cheng},
editor = {Daniel G. Schweikert},
title = {State Assignment Using Input/Output Functions},
booktitle = {Proceedings of the 29th Design Automation Conference, Anaheim, California,
USA, June 8-12, 1992},
pages = {573--577},
publisher = {{IEEE} Computer Society Press},
year = {1992},
url = {http://portal.acm.org/citation.cfm?id=113938.149632},
timestamp = {Thu, 16 Mar 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/PomeranzC92.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/eurodac/PomeranzRR92,
author = {Irith Pomeranz and
Lakshmi N. Reddy and
Sudhakar M. Reddy},
editor = {Gerald Musgrave},
title = {{SPADES:} a simulator for path delay faults in sequential circuits},
booktitle = {Proceedings of the conference on European design automation, {EURO-DAC}
'92, Hamburg, Germany, September 7-10, 1992},
pages = {428--435},
publisher = {{IEEE} Computer Society Press},
year = {1992},
url = {https://doi.org/10.1109/EURDAC.1992.246208},
doi = {10.1109/EURDAC.1992.246208},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/eurodac/PomeranzRR92.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ftcs/PomeranzR92,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {A Divide-And-Conquer Approach to Test Generation for Large Synchronous
Sequential Circuits},
booktitle = {Digest of Papers: FTCS-22, The Twenty-Second Annual International
Symposium on Fault-Tolerant Computing, Boston, Massachusetts, USA,
July 8-10, 1992},
pages = {230--237},
publisher = {{IEEE} Computer Society},
year = {1992},
url = {https://doi.org/10.1109/FTCS.1992.243579},
doi = {10.1109/FTCS.1992.243579},
timestamp = {Wed, 16 Oct 2019 14:14:57 +0200},
biburl = {https://dblp.org/rec/conf/ftcs/PomeranzR92.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ftcs/JhaPRM92,
author = {Niraj K. Jha and
Irith Pomeranz and
Sudhakar M. Reddy and
Robert J. Miller},
title = {Synthesis of Multi-Level Combinational Circuits for Complete Robust
Path Delay Fault Testability},
booktitle = {Digest of Papers: FTCS-22, The Twenty-Second Annual International
Symposium on Fault-Tolerant Computing, Boston, Massachusetts, USA,
July 8-10, 1992},
pages = {280--287},
publisher = {{IEEE} Computer Society},
year = {1992},
url = {https://doi.org/10.1109/FTCS.1992.243573},
doi = {10.1109/FTCS.1992.243573},
timestamp = {Tue, 23 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ftcs/JhaPRM92.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/PomeranzR92,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Louise Trevillyan and
Michael R. Lightner},
title = {On the generation of small dictionaries for fault location},
booktitle = {1992 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 1992, Santa Clara, CA, USA, November 8-12, 1992. Digest of
Technical Papers},
pages = {272--279},
publisher = {{IEEE} Computer Society / {ACM}},
year = {1992},
url = {https://doi.org/10.1109/ICCAD.1992.279361},
doi = {10.1109/ICCAD.1992.279361},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/PomeranzR92.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/PomeranzR92a,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Louise Trevillyan and
Michael R. Lightner},
title = {An efficient non-enumerative method to estimate path delay fault coverage},
booktitle = {1992 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 1992, Santa Clara, CA, USA, November 8-12, 1992. Digest of
Technical Papers},
pages = {560--567},
publisher = {{IEEE} Computer Society / {ACM}},
year = {1992},
url = {https://doi.org/10.1109/ICCAD.1992.279312},
doi = {10.1109/ICCAD.1992.279312},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/PomeranzR92a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ReddyPR92,
author = {Lakshmi N. Reddy and
Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Louise Trevillyan and
Michael R. Lightner},
title = {{COMPACTEST-II:} a method to generate compact two-pattern test sets
for combinational logic circuits},
booktitle = {1992 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 1992, Santa Clara, CA, USA, November 8-12, 1992. Digest of
Technical Papers},
pages = {568--574},
publisher = {{IEEE} Computer Society / {ACM}},
year = {1992},
url = {https://doi.org/10.1109/ICCAD.1992.279311},
doi = {10.1109/ICCAD.1992.279311},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/ReddyPR92.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icpp/KommuP92,
author = {Venkataramana Kommu and
Irith Pomeranz},
editor = {Quentin F. Stout},
title = {Effect of Communication in a Parallel Genetic Algorithm},
booktitle = {Proceedings of the 1992 International Conference on Parallel Processing,
University of Michigan, An Arbor, Michigan, USA, August 17-21, 1992.
Volume {III:} Algorithms {\&} Applications},
pages = {310--317},
publisher = {{CRC} Press},
year = {1992},
timestamp = {Mon, 28 Jul 2014 17:06:01 +0200},
biburl = {https://dblp.org/rec/conf/icpp/KommuP92.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/PomeranzR92,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {3-Weight Pseudo-Random Test Generation Based on a Deterministic Test
Set},
booktitle = {Proceedings of the Fifth International Conference on {VLSI} Design,
{VLSI} Design 1992, Bangalore, India, January 4-7, 1992},
pages = {148--153},
publisher = {{IEEE} Computer Society},
year = {1992},
url = {https://doi.org/10.1109/ICVD.1992.658037},
doi = {10.1109/ICVD.1992.658037},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/PomeranzR92.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/PomeranzR92,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Generalization of independent faults for transition faults},
booktitle = {10th {IEEE} {VLSI} Test Symposium (VTS'92), 7-9 Apr 1992, Atlantic
City, NJ, {USA}},
pages = {7--12},
publisher = {{IEEE} Computer Society},
year = {1992},
url = {https://doi.org/10.1109/VTEST.1992.232716},
doi = {10.1109/VTEST.1992.232716},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/PomeranzR92.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/et/PomeranzK91,
author = {Irith Pomeranz and
Zvi Kohavi},
title = {The minimum test set problem for circuits with nonreconvergent fanout},
journal = {J. Electron. Test.},
volume = {2},
number = {4},
pages = {339--349},
year = {1991},
url = {https://doi.org/10.1007/BF00135229},
doi = {10.1007/BF00135229},
timestamp = {Fri, 11 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/et/PomeranzK91.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/PomeranzK91,
author = {Irith Pomeranz and
Zvi Kohavi},
title = {Polynomial Complexity Algorithms for Increasing the Testability of
Digital Circuits by Testing Module Insertion},
journal = {{IEEE} Trans. Computers},
volume = {40},
number = {11},
pages = {1198--1214},
year = {1991},
url = {https://doi.org/10.1109/12.102824},
doi = {10.1109/12.102824},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/PomeranzK91.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/PomeranzR91,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {A. Richard Newton},
title = {On Achieving a Complete Fault Coverage for Sequential Machines Using
the Transition Fault Model},
booktitle = {Proceedings of the 28th Design Automation Conference, San Francisco,
California, USA, June 17-21, 1991},
pages = {341--346},
publisher = {{ACM}},
year = {1991},
url = {https://doi.org/10.1145/127601.127691},
doi = {10.1145/127601.127691},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/PomeranzR91.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ftcs/PomeranzR91,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Test Generation for Synchronous Sequential Circuits Using Multiple
Observation Times},
booktitle = {Proceedings of the 1991 International Symposium on Fault-Tolerant
Computing, Montreal, Canada},
pages = {52--59},
publisher = {{IEEE} Computer Society},
year = {1991},
url = {https://doi.org/10.1109/FTCS.1991.146632},
doi = {10.1109/FTCS.1991.146632},
timestamp = {Wed, 16 Oct 2019 14:14:57 +0200},
biburl = {https://dblp.org/rec/conf/ftcs/PomeranzR91.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/PomeranzR91,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Test Generation for Synchronous Sequential Circuits Based on Fault
Extraction},
booktitle = {1991 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 1993, Santa Clara, CA, USA, November 11-14, 1991. Digest of
Technical Papers},
pages = {450--453},
publisher = {{IEEE} Computer Society},
year = {1991},
url = {https://doi.org/10.1109/ICCAD.1991.185301},
doi = {10.1109/ICCAD.1991.185301},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/PomeranzR91.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/PomeranzRR91,
author = {Irith Pomeranz and
Sudhakar M. Reddy and
Lakshmi N. Reddy},
title = {Increasing Fault Coverage for Synchronous Sequential Circuits by the
Multiple Observation Time Test Strategy},
booktitle = {1991 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 1993, Santa Clara, CA, USA, November 11-14, 1991. Digest of
Technical Papers},
pages = {454--457},
publisher = {{IEEE} Computer Society},
year = {1991},
url = {https://doi.org/10.1109/ICCAD.1991.185302},
doi = {10.1109/ICCAD.1991.185302},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/PomeranzRR91.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icftcs/PomeranzR91,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
editor = {Mario Dal Cin and
Wolfgang Hohl},
title = {Testing of Fault-Tolerant Hardware},
booktitle = {Fault-Tolerant Computing Systems, Tests, Diagnosis, Fault Treatment,
5th International {GI/ITG/GMA} Conference, N{\"{u}}rnberg, Germany,
September 25-27, 1991, Proceedings},
series = {Informatik-Fachberichte},
volume = {283},
pages = {148--159},
publisher = {Springer},
year = {1991},
url = {https://doi.org/10.1007/978-3-642-76930-6\_13},
doi = {10.1007/978-3-642-76930-6\_13},
timestamp = {Wed, 17 May 2017 14:24:33 +0200},
biburl = {https://dblp.org/rec/conf/icftcs/PomeranzR91.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/PomeranzRR91,
author = {Irith Pomeranz and
Lakshmi N. Reddy and
Sudhakar M. Reddy},
title = {{COMPACTEST:} {A} Method to Generate Compact Test Sets for Combinatorial
Circuits},
booktitle = {Proceedings {IEEE} International Test Conference 1991, Test: Faster,
Better, Sooner, Nashville, TN, USA, October 26-30, 1991},
pages = {194--203},
publisher = {{IEEE} Computer Society},
year = {1991},
url = {https://doi.org/10.1109/TEST.1991.519510},
doi = {10.1109/TEST.1991.519510},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/itc/PomeranzRR91.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/PomeranzR91,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Achieving Complete Delay Fault Testability by Extra Inputs},
booktitle = {Proceedings {IEEE} International Test Conference 1991, Test: Faster,
Better, Sooner, Nashville, TN, USA, October 26-30, 1991},
pages = {273--282},
publisher = {{IEEE} Computer Society},
year = {1991},
url = {https://doi.org/10.1109/TEST.1991.519519},
doi = {10.1109/TEST.1991.519519},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/itc/PomeranzR91.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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