Volume 39, Number 1, March 2011

Volume 39, Number 2, May 2011

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  Nathan L. Binkert, Bradford M. Beckmann, Gabriel Black, Steven K. Reinhardt, Ali G. Saidi, Arkaprava Basu, Joel Hestness, Derek Hower, Tushar Krishna, Somayeh Sardashti, Rathijit Sen, Korey Sewell, Muhammad Shoaib, Nilay Vaish, Mark D. Hill, David A. Wood: The gem5 simulator. 1-7
• 
  Alexander Thomasian: Survey and analysis of disk scheduling methods. 8-25
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  Thimmarayaswamy K, Mary M. Dsouza, G. Varaprasad: Low power techniques for an android based phone. 26-35

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  Mark Thorson: Internet nuggets. 36-52

Volume 39, Number 3, June 2011

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  David A. Ferrucci: IBM's Watson/DeepQA.
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  Ravi Kannan: Algorithms: Recent Highlights and Challenges.
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  Luiz Andre Barroso: Warehouse-Scale Computing: Entering the Teenage Decade.

Volume 39, Number 4, September 2011

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  Miriam Leeser, Devon Yablonski, Dana Brooks, Laurie A. Smith King: The challenges of writing portable, correct and high performance libraries for GPUs. 2-7
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  Kuen Hung Tsoi, Wayne Luk: Power profiling and optimization for heterogeneous multi-core systems. 8-13

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  Serban Georgescu, Peter Chow: GPU accelerated CAE using open solvers and the cloud. 14-19
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  Junying Chen, Billy Y. S. Yiu, Brandon K. Hamilton, Alfred C. H. Yu, Hayden Kwok-Hay So: Design space exploration of adaptive beamforming acceleration for bedside and portable medical ultrasound imaging. 20-25
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  Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri, Takafumi Fujimoto: GPU implementation and optimization of electromagnetic simulation using the FDTD method for antenna designing. 26-31

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  Tomoyuki Nagatsuka, Yoshito Sakaguchi, Takayuki Matsumura, Kenji Kise: CoreSymphony: an efficient reconfigurable multi-core architecture. 32-37
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  Shinya Takamaeda-Yamazaki, Ryosuke Sasakawa, Yoshito Sakaguchi, Kenji Kise: An FPGA-based scalable simulation accelerator for tile architectures. 38-43

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  Kentaro Sano, Satoru Yamamoto, Yoshiaki Hatsuda: Domain-specific programmable design of scalable streaming-array for power-efficient stencil computation. 44-49
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  Takayuki Akamine, Kenta Inakagata, Yasunori Osana, Naoyuki Fujita, Hideharu Amano: An implementation of out-of-order execution system for acceleration of computational fluid dynamics on FPGAs. 50-55
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  Haisheng Liu, Smaïl Niar, Yassin Elhillali, Atika Rivenq: Embedded architecture with hardware accelerator for target recognition in driver assistance system. 56-59

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  Oliver Pell, Oskar Mencer: Surviving the end of frequency scaling with reconfigurable dataflow computing. 60-65
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  Ana Balevic, Bart Kienhuis: KPN2GPU: an approach for discovery and exploitation of fine-grain data parallelism in process networks. 66-71

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  Amila Akagic, Hideharu Amano: High speed CRC with 64-bit generator polynomial on an FPGA. 72-77
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  Shufan Yang, T. Martin McGinnity: A biologically plausible real-time spiking neuron simulation environment based on a multiple-FPGA platform. 78-81
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  Hiroomi Sawada, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi: Parallelization of the channel width search for FPGA routing. 82-85

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  Shoji Tanabe, Takuya Nagashima, Yoshiki Yamaguchi: A study of an FPGA based flexible SIMD processor. 86-89
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  Antoine Trouvé, Kazuaki Murakami: Augmenting DR-ASIP flexibility through multi-mode custom instructions. 90-93
• 
  Shinya Kubota, Minoru Watanabe: A MEMS writer system embedded for a programmable optically reconfigurable gate array. 94-97

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  Jan Fousek, Jiri Filipovic, Matus Madzin: Automatic fusions of CUDA-GPU kernels for parallel map. 98-99
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  Kohei Matsunobu, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri: A discussion on calculating eigenvalues of real symmetric tridiagonal matrices on a GPU. 100-101
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  Dominik Meyer, Bernd Klauer: Multicore reconfiguration platform an alternative to RAMPSoC. 102-103
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  Robin Bonamy, Daniel Chillet, Olivier Sentieys, Sebastien Bilavarn: Parallelism Level Impact on Energy Consumption in Reconfigurable Devices. 104-105
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  Michael Opoku Agyeman, Ali Ahmadinia: Power and area optimisation in heterogeneous 3D networks-on-chip architectures. 106-107

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  Mark Thorson: Internet nuggets. 108-117

Volume 39, Number 5, December 2011

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  Malay Das, Amitabha Sinha, Nishant Kumar Giri: High speed residue number system (RNS) based FIR filter using distributed arithmetic (DA). 1-4
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  Anindita Chakraborty, Amitabha Sinha: Conversion of binary to single-term triple base numbers for DSP applications. 5-11
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  Satrughna Singha, Aniruddha Ghosh, Amitabha Sinha: A new architecture for FPGA based implementation of conversion of binary to double base number system (DBNS) using parallel search technique. 12-18

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  Mark Thorson: Internet nuggets. 19-23

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