Volume 2,
Number 1,
2006
Embeded Processors and Systems:
Architectural Issues and Solutions for Emerging Applications
- Sandro Bartolini, Pierfrancesco Foglia, Cosimo Antonio Prete:
Embedded processors and systems: Architectural issues and solutions for emerging applications.
1-3
- Sami Yehia, Jean-Francois Collard, Olivier Temam:
Load squared: Adding logic close to memory to reduce the latency of indirect loads in embedded and general systems.
5-14
- G. Surendra, Subhasis Banerjee, S. K. Nandy:
Instruction Reuse in SPEC, media and packet processing benchmarks: A comparative study of power, performance and related microarchitectural optimizations.
15-34
- Wei Zhang:
Compiler-guided next sub-bank prediction for reducing instruction cache leakage energy.
35-48
- Seiichiri Fujii, Akihito Sakanaka, Akihiro Chiyonobu, Toshinori Sato:
A leakage-energy-reduction technique for cache memories in embedded processors.
49-55
- Aleksandar Milenkovic, Milena Milenkovic, Emil Jovanov:
An efficient runtime instruction block verification for secure embedded systems.
57-76
- Javier Verdú, Jorge García-Vidal, Mario Nemirovsky, Mateo Valero:
The impact of traffic aggregation on the memory performance of networking applications.
77-82
- Fumio Arakawa, Makoto Ishikawa, Yuki Kondo, Tatsuya Kamei, Osamu Nishii, Toshihiro Hattori:
SH-X: An embedded processor core for consumer appliances.
83-90
- Rishi Saket, Nicolas Navet:
Frame packing algorithms for automotive applications.
93-102
- Timothy W. O'Neil, Edwin Hsing-Mean Sha:
Time-constrained loop scheduling with minimal resources.
103-117
- Gang Wang, Wenrui Gong, Ryan Kastner:
Application partitioning on programmable platforms using the ant colony optimization.
119-136
Volume 2,
Number 2,
2006
Issues in embedded single-chip multicore architectures
- Sandro Bartolini, Roberto Giorgi:
Issues in Embedded Single-Chip Multicore Architectures.
137-139
- David Ródenas, Xavier Martorell, Eduard Ayguadé, Jesús Labarta, George Almási, Calin Cascaval, José G. Castaños, José E. Moreira:
Exploiting multilevel parallelism using OpenMP on a massive multithreaded architecture.
141-155
- John Oliver, Ravishankar Rao, Diana Franklin, Frederic T. Chong, Venkatesh Akella:
Synchroscalar: Evaluation of an embedded, multi-core architecture for media applications.
157-166
- Hamed Fatemi, Bart Mesman, Henk Corporaal, Twan Basten, Richard P. Kleihorst:
RC-SIMD: Reconfigurable communication SIMD architecture for image processing applications.
167-179
- Pei Gu, Uzi Vishkin:
Case study of gate-level logic simulation on an extremely fine-grained chip multiprocessor.
181-190
- Ben A. Abderazek, Sotaro Kawata, Masahiro Sowa:
Design and architecture for an embedded 32-bit QueueCore.
191-205
- Afrin Naz, Krishna M. Kavi, Wentong Li, Philip H. Sweany:
Tiny split data-caches make big performance impact for embedded applications.
207-219
- Alex Settle, Dan Connors, Enric Gibert, Antonio González:
A dynamically reconfigurable cache for multithreaded processors.
221-233
- Patrick Anthony La Fratta, James M. Baker Jr.:
Exploring power reduction options for a single-chip multiprocessor through system-level modeling.
235-247
- Haakon Dybdahl, Per Gunnar Kjeldsberg, Marius Grannæs, Lasse Natvig:
Destructive-read in embedded DRAM, impact on power consumption.
249-260
- Yul Chu, Arul Sandeep Gade, Abhishek Bhaduri:
A low-power cache scheme for embedded computing.
261-269
Volume 2,
Numbers 3-4,
2006
Best Papers of RTS' 2005
- Abdoulaye Gamatié, Thierry Gautier, Paul Le Guernic:
Synchronous design of avionic applications based on model refinement.
273-289
- Nathan Fisher, Sanjoy K. Baruah:
A fully polynomial-time approximation scheme for feasibility analysis in static-priority systems with bounded relative deadlines.
291-299
- Frédéric Ridouard, Pascal Richard, Francis Cottet, Karim Traore:
Some results on scheduling tasks with self-suspensions.
301-312
- Maxime Van Assche, Joël Goossens, Raymond R. Devillers:
Joint garbage collection and hard real-time scheduling.
313-326
- Steven Martin, Pascale Minet, Laurent George:
Improving fixed priority schedulability with dynamic priority as secondary criterion.
327-345
- Henrik Schiøler, Jens Dalsgaard Nielsen, Kim Guldstrand Larsen, Jan Jakob Jessen:
CyNC: A method for real time analysis of systems with cyclic data flows.
347-360
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