default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDIET Computers & Digital Techniques, Volume 2
Volume 2, Number 1, January 2008
- Jen-Ho Yang, Chin-Chen Chang:
Efficient residue number system iterative modular multiplication algorithm for fast modular exponentiation. 1-5 - Chang Shu, Soonhak Kwon, Kris Gaj:
FPGA accelerated multipliers over binary composite fields constructed via low hamming weight irreducible polynomials. 6-11 - Ozgur Sinanoglu
:
Construction of an adaptive scan network for test time and data volume reduction. 12-22 - Chi-Chou Kao:
Computer-aided crosstalk minimisation design for system-on-chip. 23-29 - Romanelli Lodron Zuim, José T. de Sousa, Claudionor Coelho:
Decision heuristic for Davis Putnam, Loveland and Logemann algorithm satisfiability solving based on cube subtraction. 30-39 - Vikas Chaudhary, Tai-Hua Chen, F. Sheerin, Lawrence T. Clark:
Critical race-free low-power nand match line content addressable memory tagged cache memory. 40-44 - Mehmet Fatih Akay, Constantine Katsinis:
Contention resolution on a broadcast-based distributed shared memory multiprocessor. 45-55 - Muhammad N. Marsono, M. Watheq El-Kharashi, Fayez Gebali:
Binary LNS-based naive Bayes inference engine for spam control: noise analysis and FPGA implementation. 56-62 - Jun Ho Bahn, Nader Bagherzadeh:
Design of simulation and analytical models for a 2D-meshed asymmetric adaptive router. 63-73
Volume 2, Number 2, March 2008
- Xiangrong Zhou, Peter Petrov:
Low-power and real-time address translation through arithmetic operations for virtual memory support in embedded systems. 75-85 - Xiaofan Yang, Yuan Yan Tang, Jianqiu Cao:
Embedding torus in hexagonal honeycomb torus. 86-93 - Silvia Del Pino, Daniel Chaver, Luis Piñuel, Manuel Prieto, Francisco Tirado:
Energy reduction of the fetch mechanism through dynamic adaptation. 94-107 - Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Arun Gunda:
Comparative study of centralised and distributed compatibility-based test data compression. 108-117 - Saraju P. Mohanty, Elias Kougianos, Dhiraj K. Pradhan:
Simultaneous scheduling and binding for low gate leakage nano-complementary metaloxide-semiconductor data path circuit behavioural synthesis. 118-131 - H.-T. Lin, J. C.-M. Li:
Simultaneous capture and shift power reduction test pattern generator for scan testing. 132-141 - Jong Wook Kwak, Chu Shik Jhon:
High-performance embedded branch predictor by combining branch direction history and global branch history. 142-154
Volume 2, Number 3, May 2008
- Aiman H. El-Maleh:
Test data compression for system-on-a-chip using extended frequency-directed run-length code. 155-163 - Brad Matthews, Itamar Elhanany:
Hardware architecture for high-speed real-time dynamic programming applications. 164-171 - Xiaoxuan She:
Self-routing, reconfigurable and fault-tolerant cell array. 172-183 - José L. Núñez-Yáñez, Doug A. Edwards, Antonio Marcello Coppola:
Adaptive routing strategies for fault-tolerant on-chip networks in dynamically reconfigurable systems. 184-198 - Fredy Rivera, Marcos Sánchez-Élez, Román Hermida, Nader Bagherzadeh:
Scheduling methodology for conditional execution of kernels onto multicontext reconfigurable architectures. 199-213 - Kanupriya Gulati, Mandar Waghmode, Sunil P. Khatri, Weiping Shi:
Efficient, scalable hardware engine for Boolean satisfiability and unsatisfiable core extraction. 214-229 - Takahiro Sasaki, Yuji Ichikawa, Tetsuo Hironaka, Toshiaki Kitamura, Toshio Kondo:
Evaluation of low-energy and high-performance processor using variable stages pipeline technique. 230-238 - Kuei-Chung Chang, Tien-Fu Chen:
Low-power algorithm for automatic topology generation for application-specific networks on chips. 239-249
Volume 2, Number 4, July 2008
- Andrew Byrne, Emanuel M. Popovici, William P. Marnane:
Versatile processor for GF(pm) arithmetic for use in cryptographic applications. 253-264 - Daniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors:
Time-domain interconnect characterisation flow for appropriate model segmentation. 265-274 - Erik Larsson:
Architecture for integrated test data compression and abort-on-fail testing in a multi-site environment. 275-284 - V. S. Sheeba, Elizabeth Elias:
Two-dimensional, two-channel signal-adapted filter banks. 285-294 - Kenny Johansson, Oscar Gustafsson, Lars Wanhammar:
Implementation of elementary functions for logarithmic number systems. 295-304 - Per Karlström, Andreas Ehliar, Dake Liu:
High-performance, low-latency field-programmable gate array-based floating-point adder and multiplier units in a Virtex 4. 305-313 - Ari Kulmala, Erno Salminen, Timo D. Hämäläinen:
Distributed bus arbitration algorithm comparison on FPGA-based MPEG-4 multiprocessor system on chip. 314-325
Volume 2, Number 5, September 2008
- Aiman H. El-Maleh:
Efficient test compression technique based on block merging. 327-335 - John A. Kalomiros, John N. Lygouras:
Hardware implementation of a stereo co-processor in a medium-scale field programmable gate array. 336-346 - Suresh Srinivasan, Lin Li, Martino Ruggiero, Federico Angiolini, Narayanan Vijaykrishnan, Luca Benini:
Exploring architectural solutions for energy optimisations in bus-based system-on-chip. 347-354 - Kashif Ali, Mokhtar Aboelaze, Suprakash Datta:
Energy efficient i-cache using multiple line buffers with prediction. 355-362 - Yucheng Feng, W. Zheng, Matt Francis, H. Alan Mantooth:
Model order reduction by Miller's theorem and root localisation. 363-376 - Feng Xia, Yu-Chu Tian, Youxian Sun, Jinxiang Dong:
Control-theoretic dynamic voltage scaling for embedded controllers. 377-385 - Jin Wang, Q. S. Chen, Chong Ho Lee:
Design and implementation of a virtual reconfigurable architecture for different applications of intrinsic evolvable hardware. 386-400
Volume 2, Number 6, November 2008
- S. Roman, Hortensia Mecha, Daniel Mozos, Julio Septién:
Constant complexity scheduling for hardware multitasking in two dimensional reconfigurable field-programmable gate arrays. 401-412 - Daniel Karlsson, Petru Eles, Zebo Peng:
Model validation for embedded systems using formal method-aided simulation. 413-433 - Po-Chang Tsai, Sying-Jyan Wang:
Multi-mode-segmented scan architecture with layout-aware scan chain routing for test data and test time reduction. 434-444 - Tomas Bengtsson, Shashi Kumar, Raimund Ubar, Artur Jutman, Zebo Peng:
Test methods for crosstalk-induced delay and glitch faults in network-on-chip interconnects implementing asynchronous communication protocols. 445-460 - César Pedraza, Javier Castillo, José Ignacio Martínez, Pablo Huerta, Carlos S. de La Lama:
Self-reconfigurable secure file system for embedded Linux. 461-470 - César Augusto Missio Marcon, Edson Ifarraguirre Moreno, Ney Laert Vilar Calazans, Fernando Gehm Moraes:
Comparison of network-on-chip mapping algorithms targeting low energy consumption. 471-482 - Arseni Vitkovski, Axel Jantsch, Robert Lauter, Raimo Haukilahti, Erland Nilsson:
Low-power and error protection coding for network-on-chip traffic. 483-492
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-10-22 02:18 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
