26. MICRO 1993: Austin, Texas, USA

@proceedings{DBLP:conf/micro/1993,
  title     = {Proceedings of the 26th Annual International Symposium on Microarchitecture,
               Austin, Texas, USA, November 1993},
  booktitle = {MICRO},
  publisher = {ACM/IEEE},
  year      = {1993},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

• M. Rajagopalan, Vicki H. Allan:
  Efficient scheduling of fine grain parallelism in loops. 2-11
  
• Thomas Müller:
  Employing finite automata for resource scheduling. 12-20
  
• Zhizhong Tang, Gang Chen, Chihong Zhang, Yingwei Zhang, Bogong Su, Stanley Habib:
  GPMB - software pipelining branch-intensive loops. 21-30
  
• Timothy J. Stanley, Michael Upton, Patrick Sherhart, Trevor N. Mudge, Richard B. Brown:
  A microarchitectural performance evaluation of a 3.2 Gbyte/s microprocessor bus. 31-40
  
• Andrew Wolfe, Rodney Boleyn:
  Two-ported cache alternatives for superscalar processors. 41-48
  
• Soo-Mook Moon, Kemal Ebcioglu:
  A study on the number of memory ports in multiple instruction issue machines. 49-59
  
• Barton Sano, Alvin M. Despain:
  The 16-fold way: a microparallel taxonomy. 60-69
  
• Michael Butler, Yale N. Patt:
  A comparative performance evaluation of various state maintenance mechanisms. 70-79
  
• B. Ramakrishna Rau:
  Dynamically scheduled VLIW processors. 80-92
  
• Apoorv Srivastava, Alvin M. Despain:
  Prophetic branches: a branch architecture for code compaction and efficient execution. 94-99
  
• Matthew K. Farrens, Pius Ng, Phil Nico:
  A comparision of superscalar and decoupled access/execute architectures. 100-103
  
• Lawrence Rauchwerger, Pradeep K. Dubey, Ravi Nair:
  Measuring limits of parallelism and characterizing its vulnerability to resource constraints. 105-117
  
• A. P. Wim Böhm, Walid A. Najjar, Bhanu Shankar, Lucas Roh:
  An evaluation of bottom-up and top-down thread generation techniques. 118-127
  
• Gary S. Tyson, Matthew K. Farrens:
  Techniques for extracting instruction level parallelism on MIMD architectures. 128-137
  
• Santosh G. Abraham, Rabin A. Sugumar, Daniel Windheiser, B. Ramakrishna Rau, Rajiv Gupta:
  Predictability of load/store instruction latencies. 139-152
  
• Dionisios N. Pnevmatikatos, Manoj Franklin, Gurindar S. Sohi:
  Control flow prediction for dynamic ILP processors. 153-163
  
• Tse-Yu Yeh, Yale N. Patt:
  Branch history table indexing to prevent pipeline bubbles in wide-issue superscalar processors. 164-175
  
• Mark A. Franklin, Tienyo Pan:
  Clocked and asynchronous instruction pipelines. 177-184
  
• Alessandra Costa, Alessandro De Gloria, Paolo Faraboschi, Mauro Olivieri:
  An analysis of dynamic scheduling techniques for symbolic applications. 185-191
  
• Nathalie Drach, André Seznec:
  MIDEE: smoothing branch and instruction cache miss penalties on deep pipelines. 193-201
  
• Mayan Moudgill, Keshav Pingali, Stamatis Vassiliadis:
  Register renaming and dynamic speculation: an alternative approach. 202-213
  
• Roger A. Bringmann, Scott A. Mahlke, Richard E. Hank, John C. Gyllenhaal, Wen-mei W. Hwu:
  Speculative execution exception recovery using write-back suppression. 214-223
  
• Trung A. Diep, John Paul Shen, Mike Phillip:
  EXPLORER: a retargetable and visualization-based trace-driven simulator for superscalar processors. 225-235
  
• Ing-Jer Huang, Alvin M. Despain:
  An extended classification of inter-instruction dependency and its application in automatic synthesis of pipelined processors. 236-246
  
• Richard E. Hank, Scott A. Mahlke, Roger A. Bringmann, John C. Gyllenhaal, Wen-mei W. Hwu:
  Superblock formation using static program analysis. 247-255
  
• Mark Smotherman, Shuchi Chawla II, Stan Cox, Brian A. Malloy:
  Instruction scheduling for the Motorola 88110. 257-262
  
• H. Fatih Ugurdag, Christos A. Papachristou:
  A VLIW architecture based on shifting register files. 263-268
  

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