34. ISCA 2007: San Diego, California, USA

Special purpose to warehouse computers

• David E. Shaw, Martin M. Deneroff, Ron O. Dror, Jeffrey Kuskin, Richard H. Larson, John K. Salmon, Cliff Young, Brannon Batson, Kevin J. Bowers, Jack C. Chao, Michael P. Eastwood, Joseph Gagliardo, J. P. Grossman, Richard C. Ho, Doug Ierardi, István Kolossváry, John L. Klepeis, Timothy Layman, Christine McLeavey, Mark A. Moraes, Rolf Mueller, Edward C. Priest, Yibing Shan, Jochen Spengler, Michael Theobald, Brian Towles, Stanley C. Wang:
  Anton, a special-purpose machine for molecular dynamics simulation. 1-12
  
• Xiaobo Fan, Wolf-Dietrich Weber, Luiz André Barroso:
  Power provisioning for a warehouse-sized computer. 13-23
  

Transactions and synchronization

• Colin Blundell, Joe Devietti, E. Christopher Lewis, Milo M. K. Martin:
  Making the fast case common and the uncommon case simple in unbounded transactional memory. 24-34
  
• Weirong Zhu, Vugranam C. Sreedhar, Ziang Hu, Guang R. Gao:
  Synchronization state buffer: supporting efficient fine-grain synchronization on many-core architectures. 35-45
  

Virtual caches and hierarchies

• Michael R. Marty, Mark D. Hill:
  Virtual hierarchies to support server consolidation. 46-56
  
• Kyle J. Nesbit, James Laudon, James E. Smith:
  Virtual private caches. 57-68
  

Transactions

• Chi Cao Minh, Martin Trautmann, JaeWoong Chung, Austen McDonald, Nathan Grasso Bronson, Jared Casper, Christos Kozyrakis, Kunle Olukotun:
  An effective hybrid transactional memory system with strong isolation guarantees. 69-80
  
• Jayaram Bobba, Kevin E. Moore, Haris Volos, Luke Yen, Mark D. Hill, Michael M. Swift, David A. Wood:
  Performance pathologies in hardware transactional memory. 81-91
  
• Hany E. Ramadan, Christopher J. Rossbach, Donald E. Porter, Owen S. Hofmann, Bhandari Aditya, Emmett Witchel:
  Meta^TM//TxLinux: transactional memory for an operating system. 92-103
  
• Arrvindh Shriraman, Michael F. Spear, Hemayet Hossain, Virendra J. Marathe, Sandhya Dwarkadas, Michael L. Scott:
  An integrated hardware-software approach to flexible transactional memory. 104-115
  

Networks and routers

• Pablo Abad, Valentin Puente, José-Ángel Gregorio, Pablo Prieto:
  Rotary router: an efficient architecture for CMP interconnection networks. 116-125
  
• John Kim, William J. Dally, Dennis Abts:
  Flattened butterfly: a cost-efficient topology for high-radix networks. 126-137
  
• Jongman Kim, Chrysostomos Nicopoulos, Dongkook Park, Reetuparna Das, Yuan Xie, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das:
  A novel dimensionally-decomposed router for on-chip communication in 3D architectures. 138-149
  
• Amit Kumar, Li-Shiuan Peh, Partha Kundu, Niraj K. Jha:
  Express virtual channels: towards the ideal interconnection fabric. 150-161
  

Atomic regions and fine-grained parallelism

• Sanjeev Kumar, Christopher J. Hughes, Anthony D. Nguyen:
  Carbon: architectural support for fine-grained parallelism on chip multiprocessors. 162-173
  
• Naveen Neelakantam, Ravi Rajwar, Suresh Srinivas, Uma Srinivasan, Craig B. Zilles:
  Hardware atomicity for reliable software speculation. 174-185
  

Core fusion and quantum

• Engin Ipek, Meyrem Kirman, Nevin Kirman, José F. Martínez:
  Core fusion: accommodating software diversity in chip multiprocessors. 186-197
  
• Eric Chi, Stephen A. Lyon, Margaret Martonosi:
  Tailoring quantum architectures to implementation style: a quantum computer for mobile and persistent qubits. 198-209
  

Streams to physics processors

• Xuejun Yang, Xiaobo Yan, Zuocheng Xing, Yu Deng, Jiang Jiang, Ying Zhang:
  A 64-bit stream processor architecture for scientific applications. 210-219
  
• Christopher J. Hughes, Radek Grzeszczuk, Eftychios Sifakis, Daehyun Kim, Sanjeev Kumar, Andrew Selle, Jatin Chhugani, Matthew J. Holliman, Yen-Kuang Chen:
  Physical simulation for animation and visual effects: parallelization and characterization for chip multiprocessors. 220-231
  
• Thomas Y. Yeh, Petros Faloutsos, Sanjay J. Patel, Glenn Reinman:
  ParallAX: an architecture for real-time physics. 232-243
  

Bricks, mortars, and microfluidics

• Martha Mercaldi Kim, Mojtaba Mehrara, Mark Oskin, Todd M. Austin:
  Architectural implications of brick and mortar silicon manufacturing. 244-253
  
• Ahmed M. Amin, Mithuna Thottethodi, T. N. Vijaykumar, Steven Wereley, Stephen C. Jacobson:
  Aquacore: a programmable architecture for microfluidics. 254-265
  

Memory consistency

• Thomas F. Wenisch, Anastassia Ailamaki, Babak Falsafi, Andreas Moshovos:
  Mechanisms for store-wait-free multiprocessors. 266-277
  
• Luis Ceze, James Tuck, Pablo Montesinos, Josep Torrellas:
  BulkSC: bulk enforcement of sequential consistency. 278-289
  

Power and thermal

• Bruno Diniz, Dorgival Olavo Guedes Neto, Wagner Meira Jr., Ricardo Bianchini:
  Limiting the power consumption of main memory. 290-301
  
• Francisco J. Mesa-Martinez, Joseph Nayfach-Battilana, Jose Renau:
  Power model validation through thermal measurements. 302-311
  
• Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Howard David, Zhao Zhang:
  Thermal modeling and management of DRAM memory systems. 312-322
  

Clocks, scheduling, and stores

• Abhishek Tiwari, Smruti R. Sarangi, Josep Torrellas:
  ReCycle: : pipeline adaptation to tolerate process variation. 323-334
  
• Peter G. Sassone, Jeff Rupley, Edward Brekelbaum, Gabriel H. Loh, Bryan Black:
  Matrix scheduler reloaded. 335-346
  
• Simha Sethumadhavan, Franziska Roesner, Joel S. Emer, Doug Burger, Stephen W. Keckler:
  Late-binding: enabling unordered load-store queues. 347-357
  

Memory and caches

• Jacob Leverich, Hideho Arakida, Alex Solomatnikov, Amin Firoozshahian, Mark Horowitz, Christos Kozyrakis:
  Comparing memory systems for chip multiprocessors. 358-368
  
• Naveen Muralimanohar, Rajeev Balasubramonian:
  Interconnect design considerations for large NUCA caches. 369-380
  
• Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr., Joel S. Emer:
  Adaptive insertion policies for high performance caching. 381-391
  

Experience and methodology

• Paul A. Karger:
  Performance and security lessons learned from virtualizing the alpha processor. 392-401
  
• Tejas Karkhanis, James E. Smith:
  Automated design of application specific superscalar processors: an analytical approach. 402-411
  
• Aashish Phansalkar, Ajay Joshi, Lizy Kurian John:
  Analysis of redundancy and application balance in the SPEC CPU2006 benchmark suite. 412-423
  

Control independence and prediction

• Hyesoon Kim, José A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, Robert Cohn:
  VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization. 424-435
  
• Andrew D. Hilton, Amir Roth:
  Ginger: control independence using tag rewriting. 436-447
  
• Ahmed S. Al-Zawawi, Vimal K. Reddy, Eric Rotenberg, Haitham Akkary:
  Transparent control independence (TCI). 448-459
  

Faults

• Nicholas J. Wang, Aqeel Mahesri, Sanjay J. Patel:
  Examining ACE analysis reliability estimates using fault-injection. 460-469
  
• Nidhi Aggarwal, Parthasarathy Ranganathan, Norman P. Jouppi, James E. Smith:
  Configurable isolation: building high availability systems with commodity multi-core processors. 470-481
  

Security

• Michael Dalton, Hari Kannan, Christos Kozyrakis:
  Raksha: a flexible information flow architecture for software security. 482-493
  
• Zhenghong Wang, Ruby B. Lee:
  New cache designs for thwarting software cache-based side channel attacks. 494-505
  

Vulnerabilities

• Niranjan Soundararajan, Angshuman Parashar, Anand Sivasubramaniam:
  Mechanisms for bounding vulnerabilities of processor structures. 506-515
  
• Kristen R. Walcott, Greg Humphreys, Sudhanva Gurumurthi:
  Dynamic prediction of architectural vulnerability from microarchitectural state. 516-527
  

Last update Fri May 25 08:23:43 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page