12. HPCA 2006: Austin, Texas, USA

Keynote

• Doug E. Shaw:
  New architectures for a new biology. 4
  

Chip Multiprocessors (CMPs)

• Kypros Constantinides, Stephen Plaza, Jason A. Blome, Bin Zhang, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Michael Orshansky:
  BulletProof: a defect-tolerant CMP switch architecture. 5-16
  
• Yingmin Li, Benjamin C. Lee, David Brooks, Zhigang Hu, Kevin Skadron:
  CMP design space exploration subject to physical constraints. 17-28
  
• David A. Penry, Daniel Fay, David Hodgdon, Ryan Wells, Graham Schelle, David I. August, Dan Connors:
  Exploiting parallelism and structure to accelerate the simulation of chip multi-processors. 29-40
  

Processor Architecture

• Shiliang Hu, Ilhyun Kim, Mikko H. Lipasti, James E. Smith:
  An approach for implementing efficient superscalar CISC processors. 41-52
  
• Miquel Pericàs, Adrián Cristal, Ruben Gonzalez, Daniel A. Jiménez, Mateo Valero:
  A decoupled KILO-instruction processor. 53-64
  
• Samantika Subramaniam, Gabriel H. Loh:
  Store vectors for scalable memory dependence prediction and scheduling. 65-76
  

Parallel Architecture

• Jian Li, José F. Martínez:
  Dynamic power-performance adaptation of parallel computation on chip multiprocessors. 77-87
  
• Aamer Jaleel, Matthew Mattina, Bruce L. Jacob:
  Last level cache (LLC) performance of data mining workloads on a CMP - a case study of parallel bioinformatics workloads. 88-98
  
• P. J. Joseph, Kapil Vaswani, Matthew J. Thazhuthaveetil:
  Construction and use of linear regression models for processor performance analysis. 99-108
  

Keynote

• Per Stenström:
  Chip-multiprocessing and beyond. 109
  

Energy and Power

• Nicholas Riley, Craig B. Zilles:
  Probabilistic counter updates for predictor hysteresis and stratification. 110-120
  
• Canturk Isci, Margaret Martonosi:
  Phase characterization for power: evaluating control-flow-based and event-counter-based techniques. 121-132
  
• Vivek Pandey, Weihang Jiang, Yuanyuan Zhou, Ricardo Bianchini:
  DMA-aware memory energy management. 133-144
  

Memory Systems

• Prateek Pujara, Aneesh Aggarwal:
  Increasing the cache efficiency by eliminating noise. 145-154
  
• Ravi K. Venkatesan, Stephen Herr, Eric Rotenberg:
  Retention-aware placement in DRAM (RAPID): software methods for quasi-non-volatile DRAM. 155-165
  
• Chaiyasit Manovit, Sudheendra Hangal:
  Completely verifying memory consistency of test program executions. 166-175
  

Disk and High Performance I/O

• Youngjae Kim, Sudhanva Gurumurthi, Anand Sivasubramaniam:
  Understanding the performance-temperature interactions in disk I/O of server workloads. 176-186
  
• Hao Yu, Ramendra K. Sahoo, C. Howson, G. Almasi, José G. Castaños, Manish Gupta, José E. Moreira, J. J. Parker, Thomas Engelsiepen, Robert B. Ross, Rajeev Thakur, Robert Latham, William D. Gropp:
  High performance file I/O for the Blue Gene/L supercomputer. 187-196
  

Industrial Perspectives on Challenges for Next-Generation Computer Systems

• Raj Yavatkar:
  Industrial Perspectives: Platform Design Challenges with Many cores. 201-201
  
• Renato Recio:
  Industrial Perspectives: System IO Network Evolution - Closing Requirement Gaps. 201-201
  
• Philip G. Emma:
  Industrial Perspectives: The Next Roadblocks in SOC Evolution: On-Chip Storage Capacity and Off-Chip Bandwidth. 201-201
  

Fault-Tolerant Architecture and Security

• Jun Nakano, Pablo Montesinos, Kourosh Gharachorloo, Josep Torrellas:
  ReViveI/O: efficient handling of I/O in highly-available rollback-recovery servers. 200-211
  
• Sumeet Kumar, Aneesh Aggarwal:
  Reducing resource redundancy for concurrent error detection techniques in high performance microprocessors. 212-221
  
• Weidong Shi, Joshua B. Fryman, Guofei Gu, Hsien-Hsin S. Lee, Youtao Zhang, Jun Yang:
  InfoShield: a security architecture for protecting information usage in memory. 222-231
  

Hardware/Software Tradeoffs

• Milos Prvulovic:
  CORD: cost-effective (and nearly overhead-free) order-recording and data race detection. 232-243
  
• Ruke Huang, Alok Garg, Michael C. Huang:
  Software-hardware cooperative memory disambiguation. 244-253
  
• Kevin E. Moore, Jayaram Bobba, Michelle J. Moravan, Mark D. Hill, David A. Wood:
  LogTM: log-based transactional memory. 254-265
  

Multi-Threaded Systems

• JaeWoong Chung, Hassan Chafi, Chi Cao Minh, Austen McDonald, Brian D. Carlstrom, Christos Kozyrakis, Kunle Olukotun:
  The common case transactional behavior of multithreaded programs. 266-277
  
• Alex Gontmakher, Avi Mendelson, Assaf Schuster, Gregory Shklover:
  Speculative synchronization and thread management for fine granularity threads. 278-287
  
• Joseph J. Sharkey, Dmitry V. Ponomarev:
  Efficient instruction schedulers for SMT processors. 288-298
  

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