3. FPGA 1995: Monterey, CA, USA

• Shashidhar Thakur, D. F. Wong:
  On Designing ULM-based FPGA Logic Modules. 3-9
  
• Vaughn Betz, Jonathan Rose:
  Using Architectural ``Families'' to Increase FPGA Speed and Density. 10-16
  
• Vijayshri Maheshwari, Joel Darnauer, John Ramirez, Wayne Wei-Ming Dai:
  Design of FPGAs with Area I/O for Field Programmable MCM. 17-23
  
• Charles Selvidge, Anant Agarwal, Matthew Dahl, Jonathan Babb:
  TIERS: Topology Independent Pipelined Routing and Scheduling for VirtualWire Compilation. 25-31
  
• Scott Hauck, Gaetano Borriello:
  Logic Partition Orderings for Multi-FPGA Systems. 32-38
  
• H. Pottinger, W. Eatherton, J. Kelly, T. Schiefelbein, L. R. Mullin, R. Ziegler:
  Hardware Assists for High Performance Computing Using a Mathematics of Arrays. 39-45
  
• Laurent Moll, Jean Vuillemin, Philippe Boucard:
  High-Energy Physics on DECPeRLe-1 Programmable Active Memory. 47-52
  
• Stephen D. Scott, Ashok Samal, Sharad C. Seth:
  HGA: A Hardware-Based Genetic Algorithm. 53-59
  
• Koray Öner, Luiz André Barroso, Sasan Iman, Jaeheon Jeong, Krishnan Ramamurthy, Michel Dubois:
  The Design of RPM: An FPGA-based Multiprocessor Emulator. 60-66
  
• Jason Cong, Yean-Yow Hwang:
  Simultaneous Depth and Area Minimization in LUT-based FPGA Mapping. 68-74
  
• Baher Haroun, Behzad Sajjadi:
  Synthesis of Signal Processing Structured Datapaths for FPGAs Supporting RAMs and Busses. 75-81
  
• Jason Cong, Yuzheng Ding:
  On Nominal Delay Minimization in LUT-based FPGA Technology Mapping. 82-88
  
• Nam Sung Woo:
  Revisiting the Cascade Circuit in Logic Cells of Lookup Table Based FPGAs. 90-96
  
• Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic:
  Architecture of Centralized Field-Configurable Memory. 97-103
  
• Paul Chow, P. Glenn Gulak:
  A Field-Programmable Mixed-Analog-Digital Array. 104-109
  
• Larry McMurchie, Carl Ebeling:
  PathFinder: A Negotiation-based Performance-driven Router for FPGAs. 111-117
  
• Anmol Mathur, K. C. Chen, C. L. Liu:
  Applications of Slack Neighborhood Graphs to Timing Driven Optimization Problems in FPGAs. 118-124
  
• Tong Liu, Wei-Kang Huang, Fabrizio Lombardi:
  Testing of Uncustomized Segmented Channel Field Programmable Gate Arrays. 125-131
  
• Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien:
  Spectral-Based Multi-Way FPGA Partitioning. 133-139
  
• Dennis J.-H. Huang, Andrew B. Kahng:
  Multi-way System Partitioning into a Single Type or Multiple Types of FPGAs. 140-145
  
• Kalapi Roy-Neogi, Carl Sechen:
  Multiple FPGA Partitioning with Performance Optimization. 146-152
  
• Brian Schoner, John D. Villasenor, Steve Molloy, Rajeev Jain:
  Techniques for FPGA Implementation of Video Compression Systems. 154-159
  
• H. A. Xie, Kevin E. Forward, K. M. Adams, D. Leask:
  An SBus Monitor Board. 160-166
  
• Tsuyoshi Isshiki, Wayne Wei-Ming Dai:
  High-Level Bit-Serial Datapath Synthesis for Multi-FPGA Systems. 167-173
  

Last update Tue Feb 14 03:56:19 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page