• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 317 matches

• 2020
• 
  Gongli Li, Yingying Hou, Junzhe Zhu:
  An Efficient and Fast VLIW Compression Scheme for Stream Processor. IEEE Access 8: 224817-224824 (2020)
• 
  Cyril Six, Sylvain Boulmé, David Monniaux:
  Certified and efficient instruction scheduling: application to interlocked VLIW processors. Proc. ACM Program. Lang. 4(OOPSLA): 129:1-129:29 (2020)
• 
  Lukas Gerlach, Fabian Stuckmann, Holger Blume, Guillermo Payá Vayá:
  Issue-Slot Based Predication Encoding Technique for VLIW Processors. MOCAST 2020: 1-6
• 2019
• 
  Sensen Hu, Jing Haung:
  Exploring Adaptive Cache for Reconfigurable VLIW Processor. IEEE Access 7: 72634-72646 (2019)
• 
  Keni Qiu, Yujie Zhu, Yuanchao Xu, Qirun Huo, Chun Jason Xue:
  BRLoop: Constructing balanced retimed loop to architect STT-RAM-based hybrid cache for VLIW processors. Microelectron. J. 83: 137-146 (2019)
• 
  Rafail Psiakis, Angeliki Kritikakou, Olivier Sentieys, Emmanuel Casseau:
  Run-Time Coarse-Grained Hardware Mitigation for Multiple Faults on VLIW Processors. DASIP 2019: 23-28
• 
  Andreas Bytyn, Rainer Leupers, Gerd Ascheid:
  An Application-Specific VLIW Processor with Vector Instruction Set for CNN Acceleration. ISCAS 2019: 1-5
• 
  Xuesong Su, Hui Wu, Jingling Xue:
  WCET-aware hyper-block construction for clustered VLIW processors. LCTES 2019: 110-122
• 
  Andreas Bytyn, Rainer Leupers, Gerd Ascheid:
  An Application-Specific VLIW Processor with Vector Instruction Set for CNN Acceleration. CoRR abs/1904.05106 (2019)
• 2018
• 
  Joost Hoozemans:
  Targeting static and dynamic workloads with a reconfigurable VLIW processor. Delft University of Technology, Netherlands, 2018
• 
  Xuesong Su:
  WCET-aware compilation techniques for clustered VLIW processors. University of New South Wales, Sydney, Australia, 2018
• 
  Rafail Psiakis:
  Performance Optimization Mechanisms for Fault-Resilient VLIW Processors. (Mécanismes d'optimisation des performances des processeurs VLIW à tolérance de fautes). University of Rennes 1, France, 2018
• 
  Joost Hoozemans, Jeroen van Straten, Stephan Wong:
  Increasing resource utilization in mixed-criticality systems using a polymorphic VLIW processor. J. Syst. Archit. 84: 2-11 (2018)
• 
  Anderson Luiz Sartor, Pedro Henrique Exenberger Becker, Joost Hoozemans, Stephan Wong, Antonio C. S. Beck:
  Dynamic Trade-off among Fault Tolerance, Energy Consumption, and Performance on a Multiple-Issue VLIW Processor. IEEE Trans. Multi Scale Comput. Syst. 4(3): 327-339 (2018)
• 
  Anderson Luiz Sartor, Arthur Francisco Lorenzon, Sandip Kundu, Israel Koren, Antonio C. S. Beck:
  Adaptive and polymorphic VLIW processor to optimize fault tolerance, energy consumption, and performance. CF 2018: 54-61
• 
  Guillermo Talavera, Antoni Portero, Francky Catthoor:
  Impact of Address Generation on Multimedia Embedded VLIW Processors. CISIM 2018: 417-433
• 
  Marco Spaziani Brunella, Salvatore Pontarelli, Marco Bonola, Giuseppe Bianchi:
  V- PMP: A VLIW Packet Manipulator Processor. EuCNC 2018: 1-9
• 2017
• 
  Jingchuan Dong, Taiyong Wang, Bo Li, Zhe Liu, Zhiqiang Yu:
  An FPGA-based low-cost VLIW floating-point processor for CNC applications. Microprocess. Microsystems 50: 14-25 (2017)
• 
  Roel Jordans, Lech Józwiak, Henk Corporaal, Rosilde Corvino:
  Automatic instruction-set architecture synthesis for VLIW processor cores in the ASAM project. Microprocess. Microsystems 51: 114-133 (2017)
• 
  Xuesong Su, Hui Wu, Jingling Xue:
  An Efficient WCET-Aware Instruction Scheduling and Register Allocation Approach for Clustered VLIW Processors. ACM Trans. Embed. Comput. Syst. 16(5s): 120:1-120:21 (2017)
• 
  Cuong Pham-Quoc, Binh Kieu-Do-Nguyen, Anh-Vu Dinh-Duc:
  BKVex: An Adaptable VLIW Processor and Design Framework for Reconfigurable Computing Platforms. ACOMP 2017: 39-46
• 
  Sensen Hu, Anthony Brandon, Qi Guo, Yizhuo Wang:
  Improving the Performance of Adaptive Cache in Reconfigurable VLIW Processor. ARC 2017: 3-15
• 
  Anthony Brandon, Joost Hoozemans, Jeroen van Straten, Stephan Wong:
  Exploring ILP and TLP on a Polymorphic VLIW Processor. ARCS 2017: 177-189
• 
  Wei Huang, Zhonghe Guo, Xiaohua Song, Fei Sun:
  A cluster-scalable VLIW cryptography processor with high performance and energy efficiency. ASICON 2017: 414-417
• 
  Christopher Seifert, Joachim Thiemann, Lukas Gerlach, Tobias Volkmar, Guillermo Payá Vayá, Holger Blume, Steven van de Par:
  Real-time implementation of a GMM-based binaural localization algorithm on a VLIW-SIMD processor. ICME 2017: 145-150
• 
  Rafail Psiakis, Angeliki Kritikakou, Olivier Sentieys:
  NEDA: NOP Exploitation with Dependency Awareness for Reliable VLIW Processors. ISVLSI 2017: 391-396
• 
  Marcel Brand, Frank Hannig, Alexandru Tanase, Jürgen Teich:
  Orthogonal Instruction Processing: An Alternative to Lightweight VLIW Processors. MCSoC 2017: 5-12
• 
  Rafail Psiakis, Angeliki Kritikakou, Olivier Sentieys:
  Run-time Instruction Replication for permanent and soft error mitigation in VLIW processors. NEWCAS 2017: 321-324
• 
  Joost Hoozemans, Jeroen van Straten, Stephan Wong:
  Using a polymorphic VLIW processor to improve schedulability and performance for mixed-criticality systems. RTCSA 2017: 1-9
• 2016
• 
  Mounir Bahtat, Said Belkouch, Philippe Elleaume, Philippe Le Gall:
  Instruction scheduling heuristic for an efficient FFT in VLIW processors with balanced resource usage. EURASIP J. Adv. Signal Process. 2016: 38 (2016)

skipping 287 more matches