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Publication search results
found 22 matches
- 2005
- Nigel Boston:
Pipelined IIR Filter Architecture Using Pole-Radius Minimization. J. VLSI Signal Process. 39(3): 323-331 (2005) - Bruno Bougard, M. Rullmann, Erik Brockmeyer, Liesbet Van der Perre, Francky Catthoor, Wim Dehaene:
Energy Efficient Memory Architecture for High Speed Decoding of Block Turbo-Codes with the Fang-Buda Algorithm. J. VLSI Signal Process. 39(1-2): 79-92 (2005) - Yanni Chen, Keshab K. Parhi:
On the Performance and Implementation Issues of Interleaved Single Parity Check Turbo Product Codes. J. VLSI Signal Process. 39(1-2): 35-47 (2005) - Jeongseon Euh, Jeevan Chittamuru, Wayne P. Burleson:
Power-Aware 3D Computer Graphics Rendering. J. VLSI Signal Process. 39(1-2): 15-33 (2005) - Warren J. Gross, Frank R. Kschischang, Ralf Koetter, P. Glenn Gulak:
Towards a VLSI Architecture for Interpolation-Based Soft-Decision Reed-Solomon Decoders. J. VLSI Signal Process. 39(1-2): 93-111 (2005) - Lasse Harju, Mika Kuulusa, Jari Nurmi:
Flexible Implementation of a WCDMA Rake Receiver. J. VLSI Signal Process. 39(1-2): 147-160 (2005) - Atsushi Hatabu, Takashi Miyazaki, Ichiro Kuroda:
QVGA/CIF Resolution MPEG-4 Video Codec Based on a Low-Power and General-Purpose DSP. J. VLSI Signal Process. 39(1-2): 7-14 (2005) - Yih-Chyun Jenq:
Digital Signal Processing with Interleaved ADC Systems. J. VLSI Signal Process. 39(3): 267-271 (2005) - Paraskevas Kalivas, Vassilis Vassilakis, Chris Meletis, Kiamal Z. Pekmestzi:
A New Low Latency Parallel FIR Filter Scheme. J. VLSI Signal Process. 39(3): 313-322 (2005) - Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer:
Energy Efficient VLSI Architecture for Linear Turbo Equalizer. J. VLSI Signal Process. 39(1-2): 49-62 (2005) - Miriam Leeser, Srdjan Coric, Eric L. Miller, Haiqian Yu, Marc Trepanier:
Parallel-Beam Backprojection: An FPGA Implementation Optimized for Medical Imaging. J. VLSI Signal Process. 39(3): 295-311 (2005) - Tsung-Nan Lin, Joseph Shu:
Adaptive-Hierarchical-Filtering Technique for High-Quality Magazine Image Reproduction. J. VLSI Signal Process. 39(3): 237-247 (2005) - Mahmoud Méribout, Mamoru Nakanishi:
A New Real Time Object Segmentation and Tracking Algorithm and its Parallel Hardware Architecture. J. VLSI Signal Process. 39(3): 249-266 (2005) - Puneet P. Newaskar, Raúl Blázquez, Anantha P. Chandrakasan:
A/D Precision Requirements for Digital Ultra-Wideband Radio Receivers. J. VLSI Signal Process. 39(1-2): 175-188 (2005) - Timothy W. O'Neil, Edwin Hsing-Mean Sha:
Combining Extended Retiming and Unfolding for Rate-Optimal Graph Transformation. J. VLSI Signal Process. 39(3): 273-293 (2005) - Thomas Richter, Gerhard P. Fettweis:
Interleaving on Parallel DSP Architectures. J. VLSI Signal Process. 39(1-2): 161-173 (2005) - Naresh R. Shanbhag, Keshab K. Parhi:
Guest Editorial. J. VLSI Signal Process. 39(1-2): 5-6 (2005) - Alireza Shoa, Shahram Shirani:
Run-Time Reconfigurable Systems for Digital Signal Processing Applications: A Survey. J. VLSI Signal Process. 39(3): 213-235 (2005) - Mihai Sima, Sorin Cotofana, Jos T. J. van Eijndhoven, Stamatis Vassiliadis, Kees A. Vissers:
IEEE-Compliant IDCT on FPGA-Augmented TriMedia. J. VLSI Signal Process. 39(3): 195-212 (2005) - Michael J. Thul, Frank Gilbert, Timo Vogt, Gerd Kreiselmaier, Norbert Wehn:
A Scalable System Architecture for High-Throughput Turbo-Decoders. J. VLSI Signal Process. 39(1-2): 63-77 (2005) - Tai-Lai Tung, Kung Yao:
Optimum Downlink Power Control of a DS-CDMA System via Convex Programming. J. VLSI Signal Process. 39(1-2): 133-146 (2005) - Ying Yi, Roger F. Woods, Lok-Kee Ting, C. F. N. Cowan:
High Speed FPGA-Based Implementations of Delayed-LMS Filters. J. VLSI Signal Process. 39(1-2): 113-131 (2005)
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retrieved on 2024-05-10 16:03 CEST from data curated by the dblp team
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