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Publication search results
found 53 matches
- 2011
- Khalid Latif, Amir-Mohammad Rahmani, Tiberiu Seceleanu, Hannu Tenhunen:
A low-cost processing element recovery mechanism for fault tolerant Networks-on-Chip. NORCHIP 2011: 1-4 - Muhammad Abbas, Oscar Gustafsson:
Computational and implementation complexity of polynomial evaluation schemes. NORCHIP 2011: 1-6 - Mohammed Abdulaziz, Muhammad Shakir, Ping Lu, Pietro Andreani:
A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS. NORCHIP 2011: 1-4 - Michael Opoku Agyeman, Ali Ahmadinia:
An adaptive router architecture for heterogeneous 3D Networks-on-Chip. NORCHIP 2011: 1-4 - Syed Asad Alam, Oscar Gustafsson:
Implementation of narrow-band frequency-response masking for efficient narrow transition band FIR filters on FPGAs. NORCHIP 2011: 1-4 - Syed Iftekhar Ali, Md. Shafiqul Islam:
A novel low-energy match line sensing scheme for ternary content addressable memory using charge sharing. NORCHIP 2011: 1-4 - Oskar Andersson, S. M. Yasser Sherazi, Joachim Neves Rodrigues:
Impact of switching activity on the energy minimum voltage for 65 nm sub-VT CMOS. NORCHIP 2011: 1-4 - Johanna Anteroinen, Wonjae Kim, Kari Stadius, Juha Riikonen, Harri Lipsanen, Jussi Ryynänen:
Electrical properties of CVD-graphene FETs. NORCHIP 2011: 1-4 - Andrea Bevilacqua, Pietro Andreani:
A 2.7-6.1GHz CMOS local oscillator based on frequency multiplication by 3/2. NORCHIP 2011: 1-4 - Yevgen Borokhovych, Christoph Scheytt:
10 GS/s 8-bit bipolar THA in SiGe technology. NORCHIP 2011: 1-4 - Nicolas Borup, Jonas Dindorp, Alberto Nannarelli:
FPGA implementation of decimal processors for hardware acceleration. NORCHIP 2011: 1-4 - Shahzad Ahmad Butt, Luciano Lavagno:
Model-based rapid prototyping of multirate digital signal processing algorithms. NORCHIP 2011: 1-4 - Deepak Dasalukunte, Shahid Mehmood, Viktor Öwall:
Complexity analysis of IOTA filter architectures in faster-than-Nyquist multicarrier systems. NORCHIP 2011: 1-4 - Hossein Doroud, Mahsa Ghorbanian, Reza Sabbaghi-Nadooshan:
Square topology: A novel topology for NoCs. NORCHIP 2011: 1-4 - Vivek Elangovan, Markus Dietl, Puneet Sareen:
Very high bandwidth semi-digital PLL with large operating frequency range. NORCHIP 2011: 1-6 - Luca Fanori, Pietro Andreani:
Dynamic bias schemes for class-C VCOs. NORCHIP 2011: 1-4 - Mohammed Hassan, Horst Zimmermann:
An 85dB dynamic range transimpedance amplifier in 40nm CMOS technology. NORCHIP 2011: 1-4 - Brad R. Jackson, Carlos E. Saavedra:
A divide-by-three regenerative frequency divider using a subharmonic mixer. NORCHIP 2011: 1-4 - Jiajia Jiao, Yuzhuo Fu, Jiang Jiang:
Architecture-level analysis and evaluation of transient errors on NoC. NORCHIP 2011: 1-4 - Petter Kallstrom, Oscar Gustafsson:
Magnitude scaling for increased SFDR in DDFS. NORCHIP 2011: 1-4 - Seyyed Hassan Khalilinezhad, Akram Reza, Midia Reshadi:
Yield modeling and yield-aware mapping for application specific networks-on-chip. NORCHIP 2011: 1-4 - Tero Koivisto, Esa Tiiliharju, Peter Virta:
Injection-locked superharmonic self-oscillating mixer. NORCHIP 2011: 1-4 - Olli Kursu, Timo Rahkonen:
Charge scaling 10-bit successive approximation A/D converter with reduced input capacitance. NORCHIP 2011: 1-4 - Kin Keung Lee, Håkon A. Hjortland, Tor Sverre Lande:
IR-UWB technology on next generation RFID systems. NORCHIP 2011: 1-4 - Xiaodong Liu, Vijay Viswam, Stefan Back Andersson, Johan Wernehag, Imad ud Din, Pietro Andreani:
Highly linear direct conversion receiver using customized on-chip balun. NORCHIP 2011: 1-4 - Johan Löfgren, Peter Nilsson:
On hardware implementation of radix 3 and radix 5 FFT kernels for LTE systems. NORCHIP 2011: 1-4 - Denys I. Martynenko, Gunter Fischer, Oleksiy Klymenko:
Low power programmable frequency divider for IEEE 802.15.4a standard. NORCHIP 2011: 1-4 - Reza Meraji, John B. Anderson, Henrik Sjöland, Viktor Öwall:
Transistor sizing for a 4-state current mode analog channel decoder in 65-nm CMOS. NORCHIP 2011: 1-4 - Amir H. Miremadi, Ahmad Ayatollahi, Adib Abrishamifar:
A low voltage low power CMOS analog multiplier. NORCHIP 2011: 1-4 - Anders Nejdel, Markus Törmänen, Henrik Sjöland:
A linearized 1.6-5 GHz low noise amplifier using positive feedback in 65 nm CMOS. NORCHIP 2011: 1-4
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retrieved on 2024-04-28 02:46 CEST from data curated by the dblp team
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