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Publication search results
found 103 matches
- 2024
- Kasra Ahmadi, Saeed Aghapour, Mehran Mozaffari Kermani, Reza Azarderakhsh:
Efficient Error Detection Schemes for ECSM Window Method Benchmarked on FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 32(3): 592-596 (2024) - Abdulaziz Alshaya, Sudhakar Pamarti, Christos Papavassiliou:
FPGA Crystal Oscillator Circuit Emulation Based on Wave Digital Filter. IEEE Trans. Very Large Scale Integr. Syst. 32(1): 103-115 (2024) - Isa H. Altoobaji, Ahmad Hassan, Mohamed Ali, Yves Audet, Ahmed Lakhssassi:
A Low-Power 0.68-Gbps Data Communication System for Capacitive Digital Isolator With 1.9-ns Propagation Delay. IEEE Trans. Very Large Scale Integr. Syst. 32(5): 952-956 (2024) - Jongchan An, Seung-Myeong Yu, Gwangmyeong An, Bongsu Kim, Hyunsu Jang, Sewook Hwang, Junyoung Song:
A 0.7-pJ/b 12.5-Gb/s Reference-Less Subsampling Clock and Data Recovery Circuit. IEEE Trans. Very Large Scale Integr. Syst. 32(6): 1169-1172 (2024) - Junjie An, Zhidao Zhou, Linfang Wang, Wang Ye, Weizeng Li, Hanghang Gao, Zhi Li, Jinghui Tian, Yan Wang, Hongyang Hu, Jinshan Yue, Lingyan Fan, Shibing Long, Qi Liu, Chunmeng Dou:
Write-Verify-Free MLC RRAM Using Nonbinary Encoding for AI Weight Storage at the Edge. IEEE Trans. Very Large Scale Integr. Syst. 32(2): 283-290 (2024) - Md Toufiq Hasan Anik, Jean-Luc Danger, Sylvain Guilley, Naghmeh Karimi:
On the Resiliency of Protected Masked S-Boxes Against Template Attack in the Presence of Temperature and Aging Misalignments. IEEE Trans. Very Large Scale Integr. Syst. 32(5): 911-924 (2024) - Na Bai, Xin Xiao, Yaohua Xu, Yi Wang, Liang Wang, Xinjie Zhou:
Soft-Error-Aware SRAM With Multinode Upset Tolerance for Aerospace Applications. IEEE Trans. Very Large Scale Integr. Syst. 32(1): 128-136 (2024) - Robert Balas, Alessandro Ottaviano, Luca Benini:
CV32RT: Enabling Fast Interrupt and Context Switching for RISC-V Microcontrollers. IEEE Trans. Very Large Scale Integr. Syst. 32(6): 1032-1044 (2024) - Tianyou Bao, Pengzhou He, Shi Bai, Jiafeng Xie:
TINA: TMVP-Initiated Novel Accelerator for Lightweight Ring-LWE-Based PQC. IEEE Trans. Very Large Scale Integr. Syst. 32(5): 870-882 (2024) - Manuel Brosch, Matthias Probst, Matthias Glaser, Georg Sigl:
A Masked Hardware Accelerator for Feed-Forward Neural Networks With Fixed-Point Arithmetic. IEEE Trans. Very Large Scale Integr. Syst. 32(2): 231-244 (2024) - Ke Chang, Qian Xing, Guoliang Jia, Yang Pu, Yan Wang, Yuxin Wang, Yanlong Zhang, Guohe Zhang:
An Improved DEM for Multibit DT ΣΔMs Based on Poles Splitting Technique and Segmented VQ. IEEE Trans. Very Large Scale Integr. Syst. 32(1): 200-204 (2024) - Liang Chang, Xin Zhao, Ting Yue, Xi Yang, Chenglong Li, Shuisheng Lin, Jun Zhou:
IPOCIM: Artificial Intelligent Architecture Design Space Exploration With Scalable Ping-Pong Computing-in-Memory Macro. IEEE Trans. Very Large Scale Integr. Syst. 32(2): 256-268 (2024) - Chao-Yu Chen, Yan-Siou Dai, Hao-Chiao Hong:
A Neuromorphic Spiking Neural Network Using Time-to-First-Spike Coding Scheme and Analog Computing in Low-Leakage 8T SRAM. IEEE Trans. Very Large Scale Integr. Syst. 32(5): 848-859 (2024) - Bofan Chen, Zhiqun Li, Wei Shi, Yan Yao, Zhi-Ying Xia, Bing-Yan Qiu, Hao Ji:
A 6-18-GHz 6-bit Full-360° Vector-Sum Phase Shifter With Low Error in 40-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 32(3): 530-541 (2024) - Zhuojun Chen, Wenhao Yang, Jinghang Chen, Zujun Wang, Ding Ding:
Improving Radiation Reliability of SRAM-Based Physical Unclonable Function With Self-Healing and Pre-Irradiation Masking Techniques. IEEE Trans. Very Large Scale Integr. Syst. 32(2): 372-381 (2024) - Sureum Choi, Daejin Han, Chanyeong Choi, Yeongkyo Seo:
Layout-Aware Area Optimization of Transposable STT-MRAM for a Processing-In-Memory System. IEEE Trans. Very Large Scale Integr. Syst. 32(2): 245-255 (2024) - Po-Yuan Chou, Wei-Ming Chen, Shen-Iuan Liu:
A 16-Gb/s Baud-Rate CDR Circuit With One-Tap Speculative DFE and Wide Frequency Capture Range. IEEE Trans. Very Large Scale Integr. Syst. 32(3): 480-484 (2024) - Joseph Franklin Clements, Yingjie Lao:
Reliable Hardware Watermarks for Deep Learning Systems. IEEE Trans. Very Large Scale Integr. Syst. 32(4): 752-762 (2024) - Yuan Dai, Jingyuan Li, Qilong Zhu, Yunhui Qiu, Yihan Hu, Wenbo Yin, Lingli Wang:
HETA: A Heterogeneous Temporal CGRA Modeling and Design Space Exploration via Bayesian Optimization. IEEE Trans. Very Large Scale Integr. Syst. 32(3): 505-518 (2024) - Nastaran Darabi, Maeesha Binte Hashem, Hongyi Pan, Ahmet Enis Çetin, Wilfred Gomes, Amit Ranjan Trivedi:
ADC/DAC-Free Analog Acceleration of Deep Neural Networks With Frequency Transformation. IEEE Trans. Very Large Scale Integr. Syst. 32(6): 991-1003 (2024) - Charalampos Eleftheriadis, Georgios Chatzitsompanis, Georgios Karakonstantis:
Enabling Voltage Over-Scaling in Multiplierless DSP Architectures via Algorithm-Hardware Co-Design. IEEE Trans. Very Large Scale Integr. Syst. 32(2): 219-230 (2024) - Renas Ercan, Yunjia Xia, Yunyi Zhao, Rui C. V. Loureiro, Shufan Yang, Hubin Zhao:
An Ultralow-Power Real-Time Machine Learning Based fNIRS Motion Artifacts Detection. IEEE Trans. Very Large Scale Integr. Syst. 32(4): 763-773 (2024) - Fredrik Feyling, Hampus Malmberg, Carsten Wulff, Hans-Andrea Loeliger, Trond Ytterdal:
Design and Analysis of the Leapfrog Control-Bounded A/D Converter. IEEE Trans. Very Large Scale Integr. Syst. 32(1): 79-88 (2024) - Agnimesh Ghosh, Andrei Spelman, Tze Hin Cheung, Dhanashree Boopathy, Kari Stadius, Manil Dev Gomony, Mikko Valkama, Jussi Ryynänen, Marko Kosunen, Vishnu Unnikrishnan:
Reconfigurable Signal Processing and DSP Hardware Generator for 5G and Beyond Transmitters. IEEE Trans. Very Large Scale Integr. Syst. 32(1): 4-15 (2024) - Shourya Gupta, Shuo Li, Benton H. Calhoun:
Scalable All-Analog LDOs With Reduced Input Offset Variability Using Digital Synthesis Flow in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 32(1): 190-194 (2024) - Licai Hao, Yaling Wang, Yunlong Liu, Shiyu Zhao, Xinyi Zhang, Yang Li, Wenjuan Lu, Chunyu Peng, Qiang Zhao, Yongliang Zhou, Chenghu Dai, Zhiting Lin, Xiulong Wu:
Low-Cost and Highly Robust Quadruple Node Upset Tolerant Latch Design. IEEE Trans. Very Large Scale Integr. Syst. 32(5): 883-896 (2024) - Licai Hao, Xinyi Zhang, Chenghu Dai, Qiang Zhao, Wenjuan Lu, Chunyu Peng, Yongliang Zhou, Zhiting Lin, Xiulong Wu:
Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch Based on Polarity Design and Source-Isolation Technologies. IEEE Trans. Very Large Scale Integr. Syst. 32(4): 597-608 (2024) - Xiao Hu, Zhihao Li, Zhongfeng Wang, Xianhui Lu:
ALT: Area-Efficient and Low-Latency FPGA Design for Torus Fully Homomorphic Encryption. IEEE Trans. Very Large Scale Integr. Syst. 32(4): 645-657 (2024) - Yu-Kai Huang, Saul Rodriguez:
Noise Analysis and Design Methodology of Chopper Amplifiers With Analog DC-Servo Loop for Biopotential Acquisition Applications. IEEE Trans. Very Large Scale Integr. Syst. 32(1): 55-67 (2024) - Pengcheng Huang, Yaohua Wang, Zhenyu Zhao, Daheng Yue:
CAUTS: Clock Tree Optimization via Skewed Cells With Complementary Asymmetrical Uniform Transistor Sizing. IEEE Trans. Very Large Scale Integr. Syst. 32(1): 137-149 (2024)
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