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Publication search results
found 14 matches
- 2012
- Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa:
Energy-efficient High-level Synthesis for HDR Architectures. IPSJ Trans. Syst. LSI Des. Methodol. 5: 106-117 (2012) - Hirotaka Kawashima, Gang Zeng, Hideki Takase, Masato Edahiro, Hiroaki Takada:
Efficient Algorithms for Extracting Pareto-optimal Hardware Configurations in DEPS Framework. IPSJ Trans. Syst. LSI Des. Methodol. 5: 133-142 (2012) - Walid Lafi, Didier Lattard, Ahmed Amine Jerraya:
A Stackable LTE Chip for Cost-effective 3D Systems. IPSJ Trans. Syst. LSI Des. Methodol. 5: 2-13 (2012) - Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto:
0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme. IPSJ Trans. Syst. LSI Des. Methodol. 5: 32-43 (2012) - Sungho Park, Ahmed Al-Maashri, Kevin M. Irick, Aarti Chandrashekhar, Matthew Cotter, Nandhini Chandramoorthy, Michael DeBole, Vijaykrishnan Narayanan:
System-On-Chip for Biologically Inspired Vision Applications. IPSJ Trans. Syst. LSI Des. Methodol. 5: 71-95 (2012) - Seiya Shibata, Yuki Ando, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada:
A Fast Performance Estimation Framework for System-Level Design Space Exploration. IPSJ Trans. Syst. LSI Des. Methodol. 5: 44-54 (2012) - Taiga Takata, Yusuke Matsunaga:
A Robust Algorithm for Pessimistic Analysis of Logic Masking Effects in Combinational Circuits. IPSJ Trans. Syst. LSI Des. Methodol. 5: 55-62 (2012) - Hiroyuki Tomiyama:
Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. 5: 1 (2012) - Hao Xiao, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, Yuko Nakase, Sadahiro Kimura:
Optimized Communication and Synchronization for Embedded Multiprocessors Using ASIP Methodology. IPSJ Trans. Syst. LSI Des. Methodol. 5: 118-132 (2012) - Michitarou Yabuuchi, Kazutoshi Kobayashi:
NBTI-Induced Delay Degradation Analysis of FPGA Routing Structures. IPSJ Trans. Syst. LSI Des. Methodol. 5: 143-149 (2012) - Tan Yan, Qiang Ma, Martin D. F. Wong:
Advances in PCB Routing. IPSJ Trans. Syst. LSI Des. Methodol. 5: 14-22 (2012) - Hiromine Yoshihara, Masao Yanagisawa, Nozomu Togawa:
A Fast Weighted Adder by Reducing Partial Product for Reconstruction in Super-Resolution. IPSJ Trans. Syst. LSI Des. Methodol. 5: 96-105 (2012) - Masayoshi Yoshimura, Yusuke Akamine, Yusuke Matsunaga:
An Exact Estimation Algorithm of Error Propagation Probability for Sequential Circuits. IPSJ Trans. Syst. LSI Des. Methodol. 5: 63-70 (2012) - Xiongxin Zhao, Zhixiang Chen, Xiao Peng, Dajiang Zhou, Satoshi Goto:
DVB-T2 LDPC Decoder with Perfect Conflict Resolution. IPSJ Trans. Syst. LSI Des. Methodol. 5: 23-31 (2012)
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