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Publication search results
found 14 matches
- 2019
- Ajay Krishna, Michel Le Pallec, Radu Mateescu, Ludovic Noirie, Gwen Salaün:
Rigorous design and deployment of IoT applications. FormaliSE@ICSE 2019: 21-30 - Waqar Ahmad, Shahid Ali Murtza, Osman Hasan, Sofiène Tahar:
On the formalization of importance measures using HOL theorem proving. FormaliSE@ICSE 2019: 109-118 - Omar I. Al-Bataineh, Mark Reynolds:
Epistemic model checking of distributed commit protocols with byzantine faults. FormaliSE@ICSE 2019: 51-60 - Maxime Cordy, Axel Legay, Sami Lazreg, Philippe Collet:
Towards sampling and simulation-based analysis of featured weighted automata. FormaliSE@ICSE 2019: 61-64 - Milad K. Ghale, Dirk Pattinson, Michael Norrish:
Modular synthesis of verified verifiers of computation with STV algorithms. FormaliSE@ICSE 2019: 85-94 - Dmitry Ivanov, Sibylle Schupp:
Static analysis for worst-case battery utilization. FormaliSE@ICSE 2019: 1-10 - Andreas Lööw, Magnus O. Myreen:
A proof-producing translator for verilog development in HOL. FormaliSE@ICSE 2019: 99-108 - Cláudio Belo Lourenço, Maria João Frade, Jorge Sousa Pinto:
A generalized program verification workflow based on loop elimination and SA form. FormaliSE@ICSE 2019: 75-84 - Jan Bækgaard Pedersen, Kevin Chalmers:
Verifying channel communication correctness for a multi-core cooperatively scheduled runtime using CSP. FormaliSE@ICSE 2019: 65-74 - Erick Raelijohn, Michalis Famelis, Houari A. Sahraoui:
A vision for helping developers use APIs by leveraging temporal patterns. FormaliSE@ICSE 2019: 95-98 - Daniel Ratiu, Marco Gario, Hannes Schoenhaar:
FASTEN: an open extensible framework to experiment with formal specification approaches: using language engineering to develop a multi-paradigm specification environment for NuSMV. FormaliSE@ICSE 2019: 41-50 - Hoang-Dung Tran, Patrick Musau, Diego Manzanas Lopez, Xiaodong Yang, Luan Viet Nguyen, Weiming Xiang, Taylor T. Johnson:
Parallelizable reachability analysis algorithms for feed-forward neural networks. FormaliSE@ICSE 2019: 31-40 - Beyazit Yalcinkaya, Ebru Aydin Gol:
Clock reduction in timed automata while preserving design parameters. FormaliSE@ICSE 2019: 11-20 - Stefania Gnesi, Nico Plat, Nancy A. Day, Matteo Rossi:
Proceedings of the 7th International Workshop on Formal Methods in Software Engineering, FormaliSE@ICSE 2019, Montreal, QC, Canada, May 27, 2019. IEEE / ACM 2019, ISBN 978-1-7281-3373-7 [contents]
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