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Publication search results
found 101 matches
- 2010
- Kaveh Aasaraai, Andreas Moshovos:
Design space exploration of instruction schedulers for out-of-order soft processors. FPT 2010: 385-388 - Naeem Abbas, Steven Derrien, Sanjay V. Rajopadhye, Patrice Quinton:
Accelerating HMMER on FPGA using parallel prefixes and reductions. FPT 2010: 37-44 - Bijan Alizadeh, Masahiro Fujita:
A debugging method for repairing post-silicon bugs of high performance processors in the fields. FPT 2010: 328-331 - Fakhar Anjam, Muhammad Faisal Nadeem, Stephan Wong:
A VLIW softcore processor with dynamically adjustable issue-slots. FPT 2010: 393-398 - Fakhar Anjam, Stephan Wong, Faisal Nadeem:
A multiported register file with register renaming for configurable softcore VLIW processors. FPT 2010: 403-408 - Shuichi Asano, Zheng Zhi Shun, Tsutomu Maruyama:
An FPGA implementation of full-search variable block size motion estimation. FPT 2010: 399-402 - Yan Lin Aung, Siew Kei Lam
, Thambipillai Srikanthan
:
Performance estimation framework for FPGA-based processors. FPT 2010: 413-416 - Donald G. Bailey
:
Efficient implementation of greyscale morphological filters. FPT 2010: 421-424 - Brahim Betkaoui, David B. Thomas, Wayne Luk:
Comparing performance and energy efficiency of FPGAs and GPUs for high productivity computing. FPT 2010: 94-101 - Jean-Luc Beuchat
, Eiji Okamoto, Teppei Yamazaki:
Compact implementations of BLAKE-32 and BLAKE-64 on FPGA. FPT 2010: 170-177 - Steven Birk, J. Gregory Steffan, Jason Helge Anderson:
Parallelizing FPGA placement using Transactional Memory. FPT 2010: 61-69 - João Bispo
, João M. P. Cardoso
:
On identifying and optimizing instruction sequences for dynamic compilation. FPT 2010: 437-440 - Ivo Bolsens:
FPGA platforms leading the way in the application of 'more than Moore's' technology. FPT 2010 - Stephen Brown:
Technology issues facing the world's largest integrated circuits. FPT 2010 - Assem A. M. Bsoul, Steven J. E. Wilton:
An FPGA architecture supporting dynamically controlled power gating. FPT 2010: 1-8 - Andrew van der Byl, Michael R. Inggs
, Richardt H. Wilkinson:
A many processing element framework for the Discrete Fourier Transform. FPT 2010: 425-428 - Athira Chandrasekharan, Sureshwar Rajagopalan, Guruprasad Subbarayan, Tony Frangieh, Yousef Iskander, Stephen D. Craven, Cameron D. Patterson:
Accelerating FPGA development through the automatic parallel application of standard implementation tools. FPT 2010: 53-60 - Xuezheng Chu, John McAllister:
FPGA based soft-core SIMD processing: A MIMO-OFDM Fixed-Complexity Sphere Decoder case study. FPT 2010: 479-484 - Rajeswari Devadoss, Kolin Paul, M. Balakrishnan:
A tiled programmable fabric using QCA. FPT 2010: 9-16 - Florent de Dinechin, Bogdan Pasca
:
Floating-point exponential functions for DSP-enabled FPGAs. FPT 2010: 110-117 - Michael Dittrich, Thomas B. Preußer, Rainer G. Spallek:
Solving Sudokus through an incidence matrix on an FPGA. FPT 2010: 465-469 - Suhaib A. Fahmy
:
Histogram-based probability density function estimation on FPGAs. FPT 2010: 449-453 - Pierre-Emmanuel Gaillardon, M. Haykel Ben Jamaa, Marina Reyboz, Giovanni Beneventi
, Fabien Clermidy, Luca Perniola, Ian O'Connor
:
Phase-change-memory-based storage elements for configurable logic. FPT 2010: 17-20 - Shanyuan Gao, Andrew G. Schmidt, Ron Sass:
Impact of reconfigurable hardware on accelerating MPI_Reduce. FPT 2010: 29-36 - Liangwei Ge, Zhenan Tang, Kaiyu Wang, Ming Cao, Wencong Zou, Dong Liu:
Synthesis of a unified unit for evaluating an application-specific set of elementary functions. FPT 2010: 257-260 - Glen Gibb, Nick McKeown:
OpenPipes: Making distributed hardware systems easier. FPT 2010: 381-384 - Marcel Gort, Jason Helge Anderson:
Deterministic multi-core parallel routing for FPGAs. FPT 2010: 78-86 - Tim Güneysu
:
True random number generation in block memories of reconfigurable devices. FPT 2010: 200-207 - Kyuseung Han, Jong Kyung Paek, Kiyoung Choi:
Acceleration of control flow on CGRA using advanced predicated execution. FPT 2010: 429-432 - Frank Hannig
, Moritz Schmid, Jürgen Teich, Heinz Hornegger:
A deeply pipelined and parallel architecture for denoising medical images. FPT 2010: 485-490
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retrieved on 2024-06-19 14:47 CEST from data curated by the dblp team
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