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Publication search results
found 67 matches
- 2003
- Behzad Akbarpour, Sofiène Tahar:
The Application of Formal Verification to SPW Designs. DSD 2003: 325-333 - Ahmet Akkas, Michael J. Schulte:
A Quadruple Precision and Dual Double Precision Floating-Point Multiplier. DSD 2003: 76-81 - Margarita Amor, Montserrat Bóo, Ángel del Río, Michael Wand, Wolfgang Straßer:
A New Algorithm for High-Speed Projection in Point Rendering Applications. DSD 2003: 338-345 - Mark G. Arnold:
A VLIW Architecture for Logarithmic Arithmetic. DSD 2003: 294-303 - Nizamettin Aydin, Tughrul Arslan, David R. S. Cumming:
Power/Area Analysis and Optimization of a DS-SS receiver for an Integrated Sensor Microsystem. DSD 2003: 402-407 - Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Ahsan Raja Chowdhury, Syed Mostahed Ali Chowdhury:
Reversible Logic Synthesis for Minimization of Full-Adder Circuit. DSD 2003: 50-54 - Amirali Baniasadi:
Back-End Dynamic Resource Allocation Heuristics for Power-Aware High-Performance Clustered Architectures. DSD 2003: 240-247 - Oguz Benderli, Yusuf Çagatay Tekmen, A. Neslin Ismailoglu:
A Real Time, Low Latency, FPGA Implementation of the 2-D Discrete Wavelet Transformation for Streaming Image Applications. DSD 2003: 384-391 - Marco Bera, Giovanni Danese, Ivo De Lotto, Francesco Leporati, Alvaro Spelgatti:
A Development and Simulation Environment for a Floating Point Operations FPGA Based Accelerator. DSD 2003: 173-179 - Marc Bertola, Guy Bois:
A methodology for the design of AHB bus master wrappers. DSD 2003: 90-97 - Karthikeyan Bhasyam, Kia Bazargan:
HW/SW Codesign Incorporating Edge Delays Using Dynamic Programming. DSD 2003: 264-271 - Gordon J. Brebner:
Eccentric SoC Architectures as the Future Norm. DSD 2003: 2-9 - Winthir Brunnbauer, Thomas Wild, Jürgen Foag, Nuria Pazos:
A Constructive Algorithm with Look-Ahead for Mapping and Scheduling of Task Graphs with Conditional Edges. DSD 2003: 98-103 - Gregorio Cappuccino:
Operating Region Modelling of Deep-submicron CMOS Buffers Driving Global Scope Inductive Interconnects. DSD 2003: 138-143 - Juan Manuel García Chamizo, Jerónimo Mora Pascual, Higinio Mora Mora:
Exact Numerical Processing. DSD 2003: 434-437 - Ricardo Chaves, Leonel Sousa:
RDSP: A RISC DSP based on Residue Number System. DSD 2003: 128-137 - Guilin Chen, Guangyu Chen, Ismail Kadayif, Wei Zhang, Mahmut T. Kandemir, Ibrahim Kolcu, Ugur Sezer:
Compiler-Directed Management of Instruction Accesses. DSD 2003: 459-462 - Chichyang Chen, Rui-Lin Chen, Ming-Hwa Sheu:
A Fast Additive Normalization Method for Exponential Computation. DSD 2003: 286-293 - Sung Woo Chung, Hyong-Shik Kim, Chu Shik Jhon:
Distance-aware L2 Cache Organizations for Scalable Multiprocessor Systems. DSD 2003: 24-32 - Radoslaw Czarnecki, Stanislaw Deniziak, Krzysztof Sapiecha:
An Iterative Improvement Co-synthesis Algorithm for Optimization of SOPC Architecture with Dynamically Reconfigurable FPGAs. DSD 2003: 443-446 - Václav Dvorák, Vladimír Kutálek:
A Methodology for Designing Communication Architectures for Multiprocessor SoCs. DSD 2003: 455-458 - Raquel Fernández-Ramos, Jorge Romero-Sánchez, Francisco J. Ríos-Gómez, José F. Martín-Canales:
Modelling and Simulation of a Digital IC System Using SimulPet: Application to a Speech Coding Communication IC. DSD 2003: 356-361 - Petr Fiser, Jan Hlavicka, Hana Kubátová:
FC-Min: A Fast Multi-Output Boolean Minimizer. DSD 2003: 451-454 - Om Prakash Gangwal, Johan G. W. M. Janssen, Selliah Rathnam, Erwin B. Bellers, Marc Duranton:
Understanding Video Pixel Processing Applications for Flexible Implementations. DSD 2003: 392-401 - Adam Golda, Andrzej Kos:
Temperature Influence on Power Consumption and Time Delay. DSD 2003: 378-383 - Vladimir Hahanov, Raimund Ubar, Stanley Hyduke:
Back-Traced Deductive-Parallel Fault Simulation for Digital Systems. DSD 2003: 370-377 - Mario Hilgemeier, Nicole Drechsler, Rolf Drechsler:
Fast Heuristics for the Edge Coloring of Large Graphs. DSD 2003: 230-239 - Philip K. F. Hölzenspies, Erik Schepers, Wouter Bach, Mischa Jonker, Bart Sikkes, Gerard J. M. Smit, Paul J. M. Havinga:
A Communication Model Based on an n-Dimensional Torus Architecture Using Deadlock-Free Wormhole Routing. DSD 2003: 166-172 - Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar:
Exploring Storage Organization in ASIP Synthesis. DSD 2003: 120-127 - Axel Jantsch:
NoCs: A new Contract between Hardware and Software. DSD 2003: 10-16
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