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Publication search results
found 133 matches
- 1988
- Ramón D. Acosta, Mark Alexandre, Gary Imken, Bill Read:
The Role of VHDL in the MCC CAD System. DAC 1988: 34-39 - Dan Adler:
A Dynamically-Directed Switch Model for MOS Logic Simulation. DAC 1988: 506-511 - Vishwani D. Agrawal, Kwang-Ting Cheng, Prathima Agrawal:
Contest: A Concurrent Test Generator for Sequential Circuits. DAC 1988: 84-89 - Michael H. Arnold, Walter S. Scott:
An Interactive Maze Router with Hints. DAC 1988: 672-676 - Larry M. Augustin, Benoit A. Gennart, Youm Huh, David C. Luckham, Alec G. Stanculescu:
Verification of VHDL Designs Using VAL. DAC 1988: 48-53 - Jean-Loup Baer, Meei-Chiueh Liem, Larry McMurchie, Rudolf Nottrott, Lawrence Snyder, Wayne Winder:
A Notation for Describing Multiple Views of VLSI Circuits. DAC 1988: 102-107 - Mary L. Bailey, Lawrence Snyder:
An Empirical Study of On-chip Parallelism. DAC 1988: 160-165 - Donald G. Baltus, Jonathan Allen:
SOLO: A Generator of Efficient Layouts from Optimized MOS Circuit Schematics. DAC 1988: 445-452 - Richard Barth, Louis Monier, Bertrand Serlet:
Patchwork: Layout from Schematic Annotations. DAC 1988: 250-255 - Richard Barth, Bertrand Serlet:
A Structural Representation for VLSI Design. DAC 1988: 237-242 - Richard Barth, Bertrand Serlet, Pradeep S. Sindhu:
Parameterized Schematics. DAC 1988: 243-249 - Derek L. Beatty, Randal E. Bryant:
Fast Incremental Circuit Analysis Using Extracted Hierarchy. DAC 1988: 495-500 - Daniel K. Beece, George Deibert, Georgina Papp, Frank Villante:
The IBM Engineering Verification Engine. DAC 1988: 218-224 - Thomas Bergstraesser, Jürgen Gessner, Karlheinz Hafner, Stefan Wallstab:
SMART: Tools and Methods for Synthesis of VLSI Chips with Processor Architecture. DAC 1988: 654-657 - E. Berkcan, Manuel A. d'Abreu, W. Laughton:
Analog Compilation Based on Successive Decompositions. DAC 1988: 369-375 - Inderpal S. Bhandari, Mark Hirsch, Daniel P. Siewiorek:
The Min-cut Shuffle: Toward a Solution for the Global Effect Problem of Min-cut Placement. DAC 1988: 681-685 - Robert L. Blackburn, Donald E. Thomas, Patti M. Koenig:
CORAL II: Linking Behavior and Structure in an IC Design System. DAC 1988: 529-535 - Tom Blank:
Behavioral Modeling for System Design (panel). DAC 1988: 196 - Michael Boehner:
LOGEX - an Automatic Logic Extractor Form Transistor to Gate Level for CMOS Technology. DAC 1988: 517-522 - Gaetano Borriello, Ewald Detjens:
High-Level Synthesis: Current Status and Future Directions. DAC 1988: 477-482 - David G. Boyer:
Symbolic Layout Compaction Review. DAC 1988: 383-389 - Randal E. Bryant:
CAD Tool Needs for System Designers. DAC 1988: 476 - Richard Burch, Farid N. Najm, Ping Yang, Dale E. Hocevar:
Pattern-Independent Current Estimation for Reliability Analysis of CMOS Circuits. DAC 1988: 294-299 - H. Cai:
Multi-Pads, Single Layer Power Net Routing in VLSI Circuits. DAC 1988: 183-188 - H. Cai:
Connectivity Biased Channel Construction and Ordering for Building-Block Layout. DAC 1988: 560-565 - Erik C. Carlson, Rob A. Rutenbar:
Mask Verification on the Connection Machine. DAC 1988: 134-140 - Atreyi Chakraverti, Moon-Jung Chung:
Routing Algorithm for Gate Array Macro Cells. DAC 1988: 658-662 - Sheldon S. L. Chang:
Design Automation for the Component Parts Industry. DAC 1988: 634-637 - Foong-Charn Chang, Chin-Fu Chen, Prasad Subramaniam:
An Accurate and Efficient Gate Level Delay Calculator for MOS Circuits. DAC 1988: 282-287 - Chien-Hung Chao, F. Gail Gray:
Micro-operation Perturbations in Chip Level Fault Modeling. DAC 1988: 579-582
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