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Publication search results
found 21 matches
- 2000
- Igor Benko, Jo C. Ebergen:
Composing Snippets. ASYNC 2000: 23- - Ivan Blunno, Luciano Lavagno:
Automated Synthesis of Micro-Pipelines from Behavioral Verilog HDL. ASYNC 2000: 84-92 - Alexandre V. Bystrov, D. J. Kinniment, Alexandre Yakovlev:
Priority Arbiters. ASYNC 2000: 128-137 - Tiberiu Chelcea, Steven M. Nowick:
Low-Latency Asynchronous FIFO's Using Token Rings. ASYNC 2000: 210- - Jim D. Garside, W. J. Bainbridge, Andrew Bardsley, David M. Clark, David A. Edwards, Stephen B. Furber, David W. Lloyd, Siamak Mohammadi, J. S. Pepper, Steve Temple, John V. Woods, Jianwei Liu, O. Petli:
AMULET3i - An Asynchronous System-on-Chip. ASYNC 2000: 162-175 - Oliver Hauck, A. Katoch, Sorin A. Huss:
VLSI System Design Using Asynchronous Wave Pipelines: A 0.35?m CMOS 1.5 GHz Elliptic Curve Public Key Cryptosystem Chip. ASYNC 2000: 188- - Hans M. Jacobson, Erik Brunvand, Ganesh Gopalakrishnan, Prabhakar Kudva:
High-Level Asynchronous System Design Using the ACK Framework. ASYNC 2000: 93-103 - Joep L. W. Kessels, Gerrit den Besten, Ad M. G. Peeters, Torsten Kramer, Volker Timm:
Applying Asynchronous Circuits in Contactless Smart Cards. ASYNC 2000: 36-44 - Euiseok Kim, Jeong-Gun Lee, Dong-Ik Lee:
Automatic Process-Oriented Control Circuit Generation for Asynchronous High-Level Synthesis. ASYNC 2000: 104-113 - Mike J. G. Lewis, L. E. M. Brackenbury:
An Instruction Buffer for a Low-Power DSP. ASYNC 2000: 176- - Michiel M. Ligthart, Karl Fant, Ross Smith, Alexander Taubin, Alex Kondratyev:
Asynchronous Design Using Commercial HDL Synthesis Tools. ASYNC 2000: 114- - Willem C. Mallon:
On Directed Transformations of Delay-Insensitive Specifications, Alternations and Dynamic Nondeterminism. ASYNC 2000: 12-22 - Charles E. Molnar, Ian W. Jones:
Simple Circuits that Work for Complicated Reasons. ASYNC 2000: 138-149 - Jens Muttersbach, Thomas Villiger, Wolfgang Fichtner:
Practical Design of Globally-Asynchronous Locally-Synchronous Systems. ASYNC 2000: 52- - Marco A. Peña, Jordi Cortadella, Enric Pastor, Alex Kondratyev:
Formal Verification of Safety Properties in Timed Circuits. ASYNC 2000: 2-11 - Marly Roncken, Ken S. Stevens, Rajesh Pendurkar, Shai Rotem, Parimal Pal Chaudhuri:
CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder. ASYNC 2000: 62-72 - Philip P. Shirvani, Subhasish Mitra, Jo C. Ebergen, Marly Roncken:
DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits. ASYNC 2000: 73- - Montek Singh, Steven M. Nowick:
High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic Datapaths. ASYNC 2000: 198- - George S. Taylor, Simon W. Moore, Steve Wilcox, Peter Robinson:
An On-Chip Dynamically Recalibrated Delay Line for Embedded Self-Timed Systems. ASYNC 2000: 45-51 - Fei Xia, Alexandre Yakovlev, Delong Shang, Alexandre V. Bystrov, Albert Koelmans, D. J. Kinniment:
Asynchronous Communication Mechanisms Using Self-Timed Circuits. ASYNC 2000: 150- - 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2-6 April 2000, Eilat, Israel. IEEE Computer Society 2000, ISBN 0-7695-0586-4 [contents]
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