Остановите войну!
for scientists:
default search action
Search dblp
Full-text search
- > Home
Please enter a search query
- case-insensitive prefix search: default
e.g., sig matches "SIGIR" as well as "signal" - exact word search: append dollar sign ($) to word
e.g., graph$ matches "graph", but not "graphics" - boolean and: separate words by space
e.g., codd model - boolean or: connect words by pipe symbol (|)
e.g., graph|network
Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.
Author search results
no matches
Venue search results
no matches
Refine list
refine by author
- no options
- temporarily not available
refine by venue
- no options
- temporarily not available
refine by type
- no options
- temporarily not available
refine by access
- no options
- temporarily not available
refine by year
- no options
- temporarily not available
Publication search results
found 865 matches
- 2018
- Chuandong Chen, Rongshan Wei, Shaohao Wang, Wei Hu:
Novel Verification Method for Timing Optimization Based on DPSO. VLSI Design 2018: 8258397:1-8258397:8 (2018) - Mohamed Chentouf, Zine El Abidine Alaoui Ismaili:
A Novel Net Weighting Algorithm for Power and Timing-Driven Placement. VLSI Design 2018: 3905967:1-3905967:9 (2018) - Latika Desai, Suresh Mali:
Crypto-Stego-Real-Time (CSRT) System for Secure Reversible Data Hiding. VLSI Design 2018: 4804729:1-4804729:8 (2018) - Ioannis Intzes, Hongying Meng, John Paul Cosmas:
High Data Rate FinFET On-Off Keying Transmitter for Wireless Capsule Endoscopy. VLSI Design 2018: 1757903:1-1757903:7 (2018) - Mozammel H. A. Khan, Jacqueline E. Rice:
First Steps in Creating Online Testable Reversible Sequential Circuits. VLSI Design 2018: 6153274:1-6153274:13 (2018) - Yin Li, Yu Zhang, Xiaoli Guo:
Efficient Nonrecursive Bit-Parallel Karatsuba Multiplier for a Special Class of Trinomials. VLSI Design 2018: 9269157:1-9269157:7 (2018) - Shailendra Kumar Tripathi, Mohammad Samar Ansari, Amit Mahesh Joshi:
Carbon Nanotubes-Based Digitally Programmable Current Follower. VLSI Design 2018: 1080817:1-1080817:10 (2018) - 2017
- Amir Charif, Alexandre Coelho, Nacer-Eddine Zergainoh, Michael Nicolaidis:
A Framework for Scalable TSV Assignment and Selection in Three-Dimensional Networks-on-Chips. VLSI Design 2017: 9427678:1-9427678:15 (2017) - Ting-Li Chu, Sin-Hong Yu, Chorng-Sii Hwang:
Corrigendum to "High-Accuracy Programmable Timing Generator with Wide-Range Tuning Capability". VLSI Design 2017: 6898916:1 (2017) - Yuanhui Ni, Zhiyao Gong, Weiwen Chen, Chengmo Yang, Keni Qiu:
State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers. VLSI Design 2017: 1030249:1-1030249:9 (2017) - Pablo A. Petrashin, Luis E. Toledo, Walter J. Lancioni, Piotr J. Osuch, Tinus Stander:
Oscillation-Based Test Applied to a Wideband CCII. VLSI Design 2017: 5075103:1-5075103:6 (2017) - Yu Wang, Jian Chen, Chien-In Henry Chen:
Chebyshev Bandpass Filter Using Resonator of Tunable Active Capacitor and Inductor. VLSI Design 2017: 5369167:1-5369167:12 (2017) - Xiaokun Yang, Nansong Wu, Jean H. Andrian:
Comparative Power Analysis of an Adaptive Bus Encoding Method on the MBUS Structure. VLSI Design 2017: 4914301:1-4914301:7 (2017) - 2016
- Satish S. Bhairannawar, K. B. Raja, K. R. Venugopal:
An Efficient Reconfigurable Architecture for Fingerprint Recognition. VLSI Design 2016: 9532762:1-9532762:22 (2016) - Hongmei Chen, Yong-Sheng Yin, Honghui Deng, Fujiang Lin:
A Low Complexity All-Digital Background Calibration Technique for Time-Interleaved ADCs. VLSI Design 2016: 6475932:1-6475932:8 (2016) - Lan Dai, Cheng-Ying Chen:
A 69-dB SNR 89-μW AGC for Multifrequency Signal Processing Based on Peak-Statistical Algorithm and Judgment Logic. VLSI Design 2016: 6708253:1-6708253:7 (2016) - Mamata Dalui, Biplab K. Sikdar:
A Cache System Design for CMPs with Built-In Coherence Verification. VLSI Design 2016: 8093614:1-8093614:16 (2016) - Apangshu Das, Sambhu Nath Pradhan:
Shared Reed-Muller Decision Diagram Based Thermal-Aware AND-XOR Decomposition of Logic Circuits. VLSI Design 2016: 3191286:1-3191286:14 (2016) - Yumin Hou, Hu He, Xu Yang, Deyuan Guo, Xu Wang, Jiawei Fu, Keni Qiu:
FuMicro: A Fused Microarchitecture Design Integrating In-Order Superscalar and VLIW. VLSI Design 2016: 8787919:1-8787919:12 (2016) - Abhishek Jain, Richa Gupta:
Unified and Modular Modeling and Functional Verification Framework of Real-Time Image Signal Processors. VLSI Design 2016: 7283471:1-7283471:14 (2016) - Arezoo Kamran, Zainalabedin Navabi:
Self-Healing Many-Core Architecture: Analysis and Evaluation. VLSI Design 2016: 9767139:1-9767139:17 (2016) - Neeta Pandey, Kirti Gupta, Bharat Choudhary:
New Proposal for MCML Based Three-Input Logic Implementation. VLSI Design 2016: 8712768:1-8712768:10 (2016) - Vikas K. Saini, Shamim Akhter, Tanuj Chauhan:
Implementation, Test Pattern Generation, and Comparative Analysis of Different Adder Circuits. VLSI Design 2016: 1260879:1-1260879:8 (2016) - Xingyuan Tong, Tiantian Sun:
Improved Switching Energy Reduction Approach in Low-Power SAR ADC for Bioelectronics. VLSI Design 2016: 6029254:1-6029254:6 (2016) - Weigong Zhang, Li Chao, Keni Qiu, Shaonan Zhang, Xianglong Chen:
A Novel Time Synchronization Method for Dynamic Reconfigurable Bus. VLSI Design 2016: 5752080:1-5752080:10 (2016) - 2015
- Pradeep Kumar Biswal, K. Mishra, Santosh Biswas, Hemangee K. Kapoor:
A Discrete Event System Approach to Online Testing of Speed Independent Circuits. VLSI Design 2015: 651785:1-651785:16 (2015) - Jian Chen, Chien-In Henry Chen:
Process Variation Aware Wide Tuning Band Pass Filter for Steep Roll-Off High Rejection. VLSI Design 2015: 408035:1-408035:9 (2015) - David H. K. Hoe, Xiaoyu Jin:
The Design of Low Noise Amplifiers in Deep Submicron CMOS Processes: A Convex Optimization Approach. VLSI Design 2015: 312639:1-312639:16 (2015) - Kai Huang, Peng Zhu, Rongjie Yan, Xiaolang Yan:
Functional Testbench Qualification by Mutation Analysis. VLSI Design 2015: 256474:1-256474:9 (2015) - Mahshid Mojtabavi Naeini, Chia Yee Ooi:
A Novel Scan Architecture for Low Power Scan-Based Testing. VLSI Design 2015: 264071:1-264071:13 (2015)
skipping 835 more matches
loading more results
failed to load more results, please try again later
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from , , and to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from .
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
retrieved on 2024-03-28 13:48 CET from data curated by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint