• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 384 matches

• 2020
• 
  Keerthikumara Devarajegowda, Mohammad Rahmani Fadiheh, Eshan Singh, Clark W. Barrett, Subhasish Mitra, Wolfgang Ecker, Dominik Stoffel, Wolfgang Kunz:
  Gap-free Processor Verification by S²QED and Property Generation. DATE 2020: 526-531
• 
  Omar A. Yeste Ojeda, Nolan Denman, Jacob Wegman, Stephen Wunduke:
  The SCREAM Concept for the Next-Generation Very Large Array Central Signal Processor. ISNCC 2020: 1-4
• 
  Georgios Georgakarakos, Johan Lilius:
  Recursive Task Generation for Scalable SDF Graph Execution on Multicore Processors. PDP 2020: 196-200
• 2019
• 
  Junmo Park, Yongin Kwon, Yongjun Park, Dongsuk Jeon:
  Microarchitecture-Aware Code Generation for Deep Learning on Single-ISA Heterogeneous Multi-Core Mobile Processors. IEEE Access 7: 52371-52378 (2019)
• 
  Simon McIntosh-Smith, James Price, Tom Deakin, Andrei Poenaru:
  A performance analysis of the first generation of HPC-optimized Arm processors. Concurr. Comput. Pract. Exp. 31(16) (2019)
• 
  Vladimir Mironov, Alexander A. Moskovsky, Michael D'mello, Yuri Alexeev:
  An efficient MPI/OpenMP parallelization of the Hartree-Fock-Roothaan method for the first generation of Intel® Xeon Phi™ processor architecture. Int. J. High Perform. Comput. Appl. 33(1) (2019)
• 
  Bernhard Egger, Eunjin Song, Hochan Lee, Daeyong Shin:
  Random test program generation for verification and validation of the Samsung Reconfigurable Processor. J. Syst. Archit. 97: 219-238 (2019)
• 
  Mohamed Arafa, Bahaa Fahim, Sailesh Kottapalli, Akhilesh Kumar, Lily Pao Looi, Sreenivas Mandava, Andy Rudoff, Ian M. Steiner, Bob Valentine, Geetha Vedaraman, Sujal Vora:
  Cascade Lake: Next Generation Intel Xeon Scalable Processor. IEEE Micro 39(2): 29-36 (2019)
• 
  Vanita Agarwal, Rajendrakumar A. Patil, Arunkumar B. Patki:
  Architectural Considerations for Next Generation IoT Processors. IEEE Syst. J. 13(3): 2906-2917 (2019)
• 
  Thomas Debrunner, Sajad Saeedi, Paul H. J. Kelly:
  AUKE: Automatic Kernel Code Generation for an Analogue SIMD Focal-Plane Sensor-Processor Array. ACM Trans. Archit. Code Optim. 15(4): 59:1-59:26 (2019)
• 
  Zilu Wang, Qinghui Hong, Xiaoping Wang:
  Memristive Circuit Design of Emotional Generation and Evolution Based on Skin-Like Sensory Processor. IEEE Trans. Biomed. Circuits Syst. 13(4): 631-644 (2019)
• 
  Gai Liu, Joseph Primmer, Zhiru Zhang:
  Rapid Generation of High-Qality RISC-V Processors from Functional Instruction Set Specifications. DAC 2019: 122
• 
  Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik:
  High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC Processors. ETS 2019: 1-6
• 
  Jeff Stuecheli, Scott Willenborg, William J. Starke:
  IBM's Next Generation POWER Processor. Hot Chips Symposium 2019: 1-19
• 
  Firat Kula, Berna Ors:
  Average Power Consumption Estimation and Momentary Power Consumption Profile Generation of a Softcore Processor. ICDIPC 2019: 41-46
• 
  Ruud S. Jacobs, Joyce Karreman, Jitske Botma:
  Beyond Clippy's Counsel: Word Processor Feature Underuse among the Digital Generation. ProComm 2019: 145-153
• 
  Sugako Otani, Norimasa Otsuki, Yasufumi Suzuki, Naoto Okumura, Shohei Maeda, Tomonori Yanagita, Takao Koike, Yasuhisa Shimazaki, Masao Ito, Minoru Uemura, Toshihiro Hattori, Tadaaki Yamauchi, Hiroyuki Kondo:
  A 28nm 600MHz Automotive Flash Microcontroller with Virtualization-Assisted Processor for Next-Generation Automotive Architecture Complying with ISO26262 ASIL-D. ISSCC 2019: 54-56
• 
  Yewan Wang, David Nörtershäuser, Stéphane Le Masson, Jean-Marc Menaud:
  Experimental Characterization of Variation in Power Consumption for Processors of Different Generations. iThings/GreenCom/CPSCom/SmartData 2019: 702-710
• 
  Leimeng Zhuang:
  Programmable Integrated Optical Signal Processors: Toward Next-Generation Signal Processing Engine in Communication Devices. OFC 2019: 1-31
• 
  Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik:
  High-Level Combined Deterministic and Pseudoexhuastive Test Generation for RISC Processors. CoRR abs/1908.02986 (2019)
• 2018
• 
  Amaury Graillat:
  Génération de code pour un many-core avec des contraintes temps réel fortes. (Code Generation for Multi-Core Processor with Hard Real-Time Constraints). Grenoble Alpes University, France, 2018
• 
  Shotaro Sugiyama, Hiromitsu Awano, Makoto Ikeda:
  Low Latency 256-bit $mathbb{F}_p$ ECDSA Signature Generation Crypto Processor. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(12): 2290-2296 (2018)
• 
  Elango Konguvel, Muniandi Kannan:
  A Survey on FFT/IFFT Processors for Next Generation Telecommunication Systems. J. Circuits Syst. Comput. 27(3): 1830001:1-1830001:21 (2018)
• 
  Guillermo Talavera, Antoni Portero, Francky Catthoor:
  Impact of Address Generation on Multimedia Embedded VLIW Processors. CISIM 2018: 417-433
• 
  Georgios Georgakarakos, Johan Lilius:
  Efficient Task-Based Code Generation for SDF Graph Execution on Multicore Processors. DASIP 2018: 112-117
• 
  Harichand M. V, Bharatkumar Sharma, G. Sudhakaran, V. Ashok:
  Acceleration of an Adaptive Cartesian Mesh CFD Solver in the Current Generation Processor Architectures. HiPC 2018: 153-161
• 
  Emmanuel Oyekanlu, Kevin Scoles, Paul O. Oladele:
  Arbitrary Waveform Generation for IoT and Cyber Physical Systems Communication Networks Using C28x TMS320C2000 Digital Signal Processor. ICAIT 2018: 102-109
• 
  Liangbo Xie, Wei Nie, Xiaolong Yang, Yong Wang, Mu Zhou:
  A BLF Generation Scheme with Clock Variance-Tolerance for Baseband Processor of EPC Gen2 UHF RFID Tag. ICCCS (4) 2018: 543-552
• 
  Albert Farrés, Claudia Rosas, Mauricio Hanzich, Alejandro Duran, Charles Yount:
  Performance Optimization of Fully Anisotropic Elastic Wave Propagation on 2nd Generation Intel® Xeon Phi(TM) Processors. IPDPS Workshops 2018: 1033-1042
• 
  Kathleen E. Hamilton, Catherine D. Schuman, Steven R. Young, Neena Imam, Travis S. Humble:
  Neural Networks and Graph Algorithms with Next-Generation Processors. IPDPS Workshops 2018: 1194-1203

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