• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 65 matches

• 2021
• 
  David Wolpert, Christopher J. Berry, Brian Bell, Adam Jatkowski, Jesse Surprise, John Isakson, Ofer Geva, Brian Deskin, Mark Cichanowski, Dina Hamid, Chris Cavitt, Gregory Fredeman, Dinesh Kannambadi, Anthony Saporito, Ashutosh Mishra, Alper Buyuktosunoglu, Tobias Webel, Preetham Lobo, Ramon Bertran, Pradeep Bhadravati Parashurama, Dureseti Chidambarrao, Brandon Bruen, Alan P. Wagstaff, Eric Lukes, Sean M. Carey, Hunter F. Shi, Michael Romain, Paul Logsdon, Ishita Agarwal:
  Cores, Cache, Content, and Characterization: IBM's Second Generation 14-nm Product, z15. IEEE J. Solid State Circuits 56(1): 98-111 (2021)
• 2020
• 
  Sai Li, Jianwei Han, Rui Chen, Shipeng Shangguan, Yingqi Ma, Xuan Wang:
  Study on the single-event upset sensitivity of 65-nm CMOS sequential logic circuit. IEICE Electron. Express 17(10): 20200102 (2020)
• 
  Liang Wen, Longmei Nan, Jing Zhang, Chunning Meng, Yan Lu, Shiqian Qi, Jianping Lv, Yuejun Zhang:
  65 nm sub-threshold logic standard cell library using quasi-Schmitt-trigger design scheme and inverse narrow width effect aware sizing. IET Circuits Devices Syst. 14(3): 303-310 (2020)
• 
  Jingcheng Wang, Xiaowei Wang, Charles Eckert, Arun Subramaniyan, Reetuparna Das, David T. Blaauw, Dennis Sylvester:
  A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing. IEEE J. Solid State Circuits 55(1): 76-86 (2020)
• 
  Rohit Grover, T. Acosta, C. AnDyke, Emre Armagan, C. Auth, Sunny Chugh, K. Downes, M. Hattendorf, N. Jack, S. Joshi, R. Kasim, Gerald S. Leatherman, S.-H. Lee, C.-Y. Lin, A. Madhavan, H. Mao, A. Lowrie, G. Martin, G. McPherson, P. Nayak, A. Neale, D. Nminibapiel, Benjamin Orr, James Palmer, C. M. Pelto, S. S. Poon, I. Post, T. Pramanik, A. Rahman, S. Ramey, N. Seifert, K. Sethi, Anthony Schmitz, H. Wu, A. Yeoh:
  A Reliability Overview of Intel's 10+ Logic Technology. IRPS 2020: 1-6
• 
  Motoi Ichihashi, Jia Zeng, Youngtag Woo, Xuelian Zhu, Chenchen Wang, James Mazza:
  Performance Boost Scheme with Activated Dummy Fin in 12-nm FinFET Technology for High-Performance Logic Application. ISQED 2020: 196
• 
  Semiu A. Olowogemo, Ahmed Yiwere, Bor-Tyng Lin, Hao Qiu, William H. Robinson, Daniel B. Limbrick:
  Electrical Masking Improvement with Standard Logic Cell Synthesis Using 45 nm Technology Node. MWSCAS 2020: 619-622
• 2019
• 
  Juntao Wang, Pengfei He, Yan-Hong She:
  Monadic NM-algebras. Log. J. IGPL 27(6): 812-835 (2019)
• 
  Yi-Chun Shih, Chia-Fu Lee, Yen-An Chang, Po-Hao Lee, Hon-Jarn Lin, Yu-Lin Chen, Ku-Feng Lin, Ta-Ching Yeh, Hung-Chang Yu, Harry Chuang, Yu-Der Chih, Tsung-Yung Jonathan Chang:
  Logic Process Compatible 40-nm 16-Mb, Embedded Perpendicular-MRAM With Hybrid-Resistance Reference, Sub- $\mu$ A Sensing Resolution, and 17.5-nS Read Access Time. IEEE J. Solid State Circuits 54(4): 1029-1038 (2019)
• 
  Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander Fish:
  An 88-fJ/40-MHz [0.4 V]-0.61-pJ/1-GHz [0.9 V] Dual-Mode Logic 8 × 8 bit Multiplier Accumulator With a Self-Adjustment Mechanism in 28-nm FD-SOI. IEEE J. Solid State Circuits 54(2): 560-568 (2019)
• 
  Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura:
  QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS. IEEE J. Solid State Circuits 54(1): 186-196 (2019)
• 
  Yun Yin, Yiting Zhu, Liang Xiong, Wei Luo, Bowen Chen, Tong Li, Na Yan, Hongtao Xu:
  A Compact Transformer-Combined Polar/Quadrature Reconfigurable Digital Power Amplifier in 28-nm Logic LP CMOS. IEEE J. Solid State Circuits 54(3): 709-719 (2019)
• 
  Daniel Morrison, Dennis Delic, Mehmet Rasit Yuce, Jean-Michel Redoute:
  Multistage Linear Feedback Shift Register Counters With Reduced Decoding Logic in 130-nm CMOS for Large-Scale Array Applications. IEEE Trans. Very Large Scale Integr. Syst. 27(1): 103-115 (2019)
• 
  Moon-Chul Choi, Haram Ju, Han-Gon Ko, Deog-Kyoon Jeong:
  A Design of Data Path Based on CMOS Logic for a 72-Gb/s PAM-4 Transmitter in 28-nm CMOS. ICEIC 2019: 1-4
• 
  Jun Furuta, Yuto Tsukita, Kodai Yamada, Mitsunori Ebara, Kentaro Kojima, Kazutoshi Kobayashi:
  Impact of Combinational Logic Delay for Single Event Upset on Flip Flops in a 65 nm FDSOI Process. IRPS 2019: 1-4
• 
  Mitsuhiko Igarashi, Yuuki Uchida, Yoshio Takazawa, Makoto Yabuuchi, Yasumasa Tsukamoto, Koji Shibutani:
  Study of Local BTI Variation and its Impact on Logic Circuit and SRAM in 7 nm Fin-FET Process. IRPS 2019: 1-6
• 
  Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander Fish:
  Live Demo: An 88fJ / 40 MHz [0.4V] - 0.61pJ / 1GHz [0.9V] Dual Mode Logic 8×8-Bit Multiplier Accumulator with a Self-Adjustment Mechanism in 28 nm FD-SOI. ISCAS 2019: 1
• 
  Joao Pedro Cerqueira, Jieyu Li, Jiangyi Li, Weifeng He, Mingoo Seok:
  A Femto/Pico-Watt Feedforward Leakage Self-Suppression Logic Family in 180 nm to 28 nm Technologies. MWSCAS 2019: 1049-1052
• 
  Ramakant Ramakant, Sanjay Vidhyadharan, A. Krishna Shyam, Mohit P. Hirpara, Tanmay Chaudhary, Surya Shankar Dan:
  Novel Low and High Threshold TFET Based NTI and PTI Cells Benchmarked with Standard 45 nm CMOS Technology for Ternary Logic Applications. VLSI Design 2019: 419-424
• 
  Bart Bogaerts, Esra Erdem, Paul Fodor, Andrea Formisano, Giovambattista Ianni, Daniela Inclezan, Germán Vidal, Alicia Villanueva, Marina De Vos, Fangkai Yang:
  Proceedings 35th International Conference on Logic Programming (Technical Communications), ICLP 2019 Technical Communications, Las Cruces, NM, USA, September 20-25, 2019. EPTCS 306, 2019 [contents]
• 2018
• 
  S. Badrudduza, G. Abeln, T. Jew, P. Grudowski, A. Roy, C. Cavins:
  Automotive Reliable Memories Integrated into an Ultra-Low Power 40 nm CMOS Logic Process. J. Low Power Electron. 14(3): 393-403 (2018)
• 
  Yuejun Zhang, Dailu Ding, Zhao Pan, Pengjun Wang, Qiaoyan Yu:
  An ultra-low power multiplier using multi-valued adiabatic logic in 65 nm CMOS process. Microelectron. J. 78: 26-34 (2018)
• 
  Robert Giterman, Alexander Fish, Andreas Burg, Adam Teman:
  A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(4): 1245-1256 (2018)
• 
  Semiu A. Olowogemo, William H. Robinson, Daniel B. Limbrick:
  Effects of Voltage and Temperature Variations on the Electrical Masking Capability of Sub-65 nm Combinational Logic Circuits. DFT 2018: 1-6
• 
  Haruki Mori, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
  28-nm FD-SOI Dual-Port SRAM with MSB-Based Inversion Logic for Low-Power Deep Learning. ICECS 2018: 161-164
• 
  F. Griggio, James Palmer, F. Pan, N. Toledo, Anthony Schmitz, I. Tsameret, R. Kasim, Gerald S. Leatherman, J. Hicks, A. Madhavan, J. Shin, J. Steigerwald, A. Yeoh, C. Auth:
  Reliability of dual-damascene local interconnects featuring cobalt on 10 nm logic technology. IRPS 2018: 6
• 
  Taiki Uemura, Soonyoung Lee, Dahye Min, Ihlhwa Moon, Jungman Lim, Seungbae Lee, Hyun-Chul Sagong, Sangwoo Pae:
  Investigation of alpha-induced single event transient (SET) in 10 nm FinFET logic circuit. IRPS 2018: 1
• 2017
• 
  Yuan Du, Yong Ye, Weiliang Jing, Xiaoyun Li, Zhitang Song, Bomy Chen:
  Logic area reduction using the deep trench isolation technique based on 40 nm embedded PCM process. IEICE Electron. Express 14(15): 20170628 (2017)
• 
  Michael Gautschi, Michael Schaffner, Frank K. Gürkaynak, Luca Benini:
  An Extended Shared Logarithmic Unit for Nonlinear Function Kernel Acceleration in a 65-nm CMOS Multicore Cluster. IEEE J. Solid State Circuits 52(1): 98-112 (2017)
• 
  Jubal Saji, Shoaib Kamal:
  GDI logic implementation of uniform sized CSLA architectures in 45 nm SOI technology. Microprocess. Microsystems 49: 18-27 (2017)

skipping 35 more matches