• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 316 matches

• 2020
• 
  Sunsoo Kim, Vaishnav Tadiparthi, Raktim Bhattacharya:
  Nonlinear Attitude Estimation for Small UAVs with Low Power Microprocessors. ACC 2020: 2593-2598
• 
  Jinwei Zhang, Sheriff Sadiqbatcha, Wentian Jin, Sheldon X.-D. Tan:
  Accurate Power Density Map Estimation for Commercial Multi-Core Microprocessors. DATE 2020: 1085-1090
• 
  Nagabhushan Reddy, Sankaran Menon, Prashant D. Joshi:
  Validation Challenges in Recent Trends of Power Management in Microprocessors. DFT 2020: 1-6
• 
  Muhammad Arsath K. F, Vinod Ganesan, Rahul Bodduna, Chester Rebeiro:
  PARAM: A Microprocessor Hardened for Power Side-Channel Attack Resistance. HOST 2020: 23-34
• 
  Jawad Haj-Yahya, Mohammed Alser, Jeremie S. Kim, Lois Orosa, Efraim Rotem, Avi Mendelson, Anupam Chattopadhyay, Onur Mutlu:
  FlexWatts: A Power- and Workload-Aware Hybrid Power Delivery Network for Energy-Efficient Microprocessors. MICRO 2020: 1051-1066
• 
  Sunsoo Kim, Vaishnav Tadiparthi, Raktim Bhattacharya:
  Nonlinear Attitude Estimation for Small UAVs with Low Power Microprocessors. CoRR abs/2003.13802 (2020)
• 
  Sunsoo Kim, Vaishnav Tadiparthi, Raktim Bhattacharya:
  Extended H2 Filtering for Attitude Estimation in Low Power Microprocessors. CoRR abs/2006.14385 (2020)
• 
  Jawad Haj-Yahya, Mohammed Alser, Jeremie S. Kim, Lois Orosa, Efraim Rotem, Avi Mendelson, Anupam Chattopadhyay, Onur Mutlu:
  FlexWatts: A Power- and Workload-Aware Hybrid Power Delivery Network for Energy-Efficient Microprocessors. CoRR abs/2009.09094 (2020)
• 
  Zhendong Ai, Zihan Wang, Wei Cui:
  Low-Power Wireless Wearable ECG Monitoring Chestbelt Based on Ferroelectric Microprocessor. CoRR abs/2012.02290 (2020)
• 2019
• 
  Spandana Rachamalla, Shashidhar Reddy, Arun Joseph:
  Heterogeneity aware power abstractions for dynamic power dominated FinFET-based microprocessors. IET Comput. Digit. Tech. 13(6): 524-531 (2019)
• 
  Monir Zaman, Mustafa M. Shihab, Ayse K. Coskun, Yiorgos Makris:
  CAPE: A cross-layer framework for accurate microprocessor power estimation. Integr. 68: 87-98 (2019)
• 
  Tianyu Jia, Russ Joseph, Jie Gu:
  An Instruction-Driven Adaptive Clock Management Through Dynamic Phase Scaling and Compiler Assistance for a Low Power Microprocessor. IEEE J. Solid State Circuits 54(8): 2327-2338 (2019)
• 
  Sergey I. Malkovsky, Aleksei A. Sorokin, Sergey P. Korolev, A. A. Zatsarinnyi, G. I. Tsoi:
  Performance Evaluation of a Hybrid Computer Cluster Built on IBM POWER8 Microprocessors. Program. Comput. Softw. 45(6): 324-332 (2019)
• 
  Jawad Haj-Yahya, Efraim Rotem, Avi Mendelson, Anupam Chattopadhyay:
  A Comprehensive Evaluation of Power Delivery Schemes for Modern Microprocessors. ISQED 2019: 123-130
• 
  Daniel Ernesto Mera-Romo, Rafael A. Rodríguez-Solís:
  Low Power and Miniaturized Back-End Processing System for an L-Band Radiometer based on ARM Embedded Microprocessor. RWS 2019: 1-4
• 
  Muhammad Arsath K. F, Vinod Ganesan, Rahul Bodduna, Chester Rebeiro:
  PARAM: A Microprocessor Hardened for Power Side-Channel Attack Resistance. CoRR abs/1911.08813 (2019)
• 2018
• 
  Glenn Coates:
  A syntax directed imperative language microprocessor for reduced power consumption and improved performance. University of York, UK, 2018
• 
  Sai Manoj P. D., Axel Jantsch, Muhammad Shafique:
  SmartDPM: Machine Learning-Based Dynamic Power Management for Multi-Core Microprocessors. J. Low Power Electron. 14(4): 460-474 (2018)
• 
  Alberto Leva, Federico Terraneo, Irene Giacomello, William Fornaciari:
  Event-Based Power/Performance-Aware Thermal Management for High-Density Microprocessors. IEEE Trans. Control. Syst. Technol. 26(2): 535-550 (2018)
• 
  Tianyu Jia, Russ Joseph, Jie Gu:
  An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor. ESSCIRC 2018: 94-97
• 
  S. G. Solovyov, E. R. Milutin, V. A. Ryzhikov:
  Improvement of the Design of a Microprocessor-Based Power Supply Control System of an Internal Combustion Engine. EWDTS 2018: 1-4
• 
  Monir Zaman, Mustafa M. Shihab, Ayse K. Coskun, Yiorgos Makris:
  Towards a Cross-Layer Framework for Accurate Power Modeling of Microprocessor Designs. PATMOS 2018: 229-236
• 2017
• 
  Wei Wang:
  An improved instruction-level power and energy model for RISC microprocessors. University of Southampton, UK, 2017
• 
  Diary R. Sulaiman, Ibrahim Hamarash, Muhammed A. Ibrahim:
  Adaptive supply and body voltage control for ultra-low power microprocessors. IEICE Electron. Express 14(12): 20170306 (2017)
• 
  Diary R. Sulaiman, Ibrahim Hamarash, Muhammed A. Ibrahim:
  Microprocessors optimal power dissipation using combined threshold hopping and voltage scaling. IEICE Electron. Express 14(24): 20171046 (2017)
• 
  Sungkyung Park, Chester Sungchung Park:
  Design of Low-Gate-Count Low-Power Microprocessors with High Code Density for Deeply Embedded Applications. J. Circuits Syst. Comput. 26(9): 1750132:1-1750132:24 (2017)
• 
  Sriram Sundaram, Aaron Grenat, Samuel Naffziger, Tom Burd, Stephen Kosonocky, Steven Liepe, Ravinder Rachala, Miguel Rodriguez, Michael Austin, Sriram Sambamurthy:
  Bristol Ridge: A 28-nm × 86 Performance-Enhanced Microprocessor Through System Power Management. IEEE J. Solid State Circuits 52(1): 89-97 (2017)
• 
  Retraction notice to 'Power Modeling for High Performance Network-on-Chip Architectures' [Microprocessors and Microsystems 50 (2017) 80-89]. Microprocess. Microsystems 50 (2017)
• 
  Martin Omaña, Marco Padovani, Kreshnik Veliu, Cecilia Metra, Juergen Alt, Rajesh Galivanche:
  New Approaches for Power Binning of High Performance Microprocessors. IEEE Trans. Computers 66(7): 1159-1171 (2017)
• 
  Dipanjan Bhadra, Kenneth S. Stevens:
  Design of a low power, relative timing based asynchronous MSP430 microprocessor. DATE 2017: 794-799

skipping 286 more matches