• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 26 matches

• 2020
• 
  Cheng-Xin Xue, Ting-Wei Chang, Tung-Cheng Chang, Hui-Yao Kao, Yen-Cheng Chiu, Chun-Ying Lee, Ya-Chin King, Chrong Jung Lin, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Wei-Hao Chen, Meng-Fan Chang, Je-Syu Liu, Jia-Fang Li, Wei-Yu Lin, Wei-En Lin, Jing-Hong Wang, Wei-Chen Wei, Tsung-Yuan Huang:
  Embedded 1-Mb ReRAM-Based Computing-in- Memory Macro With Multibit Input and Weight for CNN-Based AI Edge Processors. IEEE J. Solid State Circuits 55(1): 203-215 (2020)
• 2019
• 
  Hossein Valavi, Peter J. Ramadge, Eric Nestler, Naveen Verma:
  A 64-Tile 2.4-Mb In-Memory-Computing CNN Accelerator Employing Charge-Domain Compute. IEEE J. Solid State Circuits 54(6): 1789-1799 (2019)
• 
  Marcella Carissimi, R. Mukherjee, Vivek Tyagi, F. Disegni, D. Manfrè, C. Torti, Daniele Gallinari, S. Rossi, A. Gambero, Donatella Brambilla, P. Zuliani, Riccardo Zurla, Alessandro Cabrini, Guido Torelli, Marco Pasotti, Chantal Auricchio, Emanuela Calvetti, Laura Capecchi, Luigi Croce, S. Zanchi, Vikas Rana, P. Mishra:
  2-Mb Embedded Phase Change Memory With 16-ns Read Access Time and 5-Mb/s Write Throughput in 90-nm BCD Technology for Automotive Applications. ESSCIRC 2019: 135-138
• 2018
• 
  Jinshun Bi, Yuan Duan, Kai Xi, Bo Li:
  Total ionizing dose and single event effects of 1 Mb HfO₂-based resistive-random-access memory. Microelectron. Reliab. 88-90: 891-897 (2018)
• 
  Mino Kim, Joo-Hyung Chae, Sungphil Choi, Gi-Moon Hong, Hyeongjun Ko, Deog-Kyoon Jeong, Suhwan Kim:
  A 4266 Mb/s/pin LPDDR4 Interface With An Asynchronous Feedback CTLE and An Adaptive 3-Step Eye Detection Algorithm for Memory Controller. IEEE Trans. Circuits Syst. II Express Briefs 65-II(12): 1894-1898 (2018)
• 
  Md Jubaer Hossain Pantho, Joel Mandebi Mbongue, Christophe Bobda, David Andrews, Marjan Asadinia:
  Enabling Transparent Acceleration of OpenCV Library Kernels on a Hybrid Memory Cube Computer. FCCM 2018: 217
• 
  Md Jubaer Hossain Pantho, Joel Mandebi Mbongue, Christophe Bobda, David Andrews:
  Transparent Acceleration of Image Processing Kernels on FPGA-Attached Hybrid Memory Cube Computers. FPT 2018: 342-345
• 2015
• 
  Ki-Tae Park, Sangwan Nam, Dae-Han Kim, Pansuk Kwak, Doosub Lee, Yoon-Hee Choi, Myung-Hoon Choi, Dong-Hun Kwak, Doo-Hyun Kim, Minsu Kim, Hyun Wook Park, Sang-Won Shim, Kyung-Min Kang, Sang-Won Park, Kangbin Lee, Hyun-Jun Yoon, Kuihan Ko, Dong-Kyo Shim, Yang-Lo Ahn, Jinho Ryu, Donghyun Kim, Kyunghwa Yun, Joonsoo Kwon, Seunghoon Shin, Dae-Seok Byeon, Kihwan Choi, Jin-Man Han, Kyehyun Kyung, Jeong-Hyuk Choi, Kinam Kim:
  Three-Dimensional 128 Gb MLC Vertical nand Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming. IEEE J. Solid State Circuits 50(1): 204-213 (2015)
• 2014
• 
  Fengying Qiao, Liyang Pan, Xiao Yu, Haozhi Ma, Dong Wu, Jun Xu:
  Total ionizing radiation effects of 2-T SONOS for 130 nm/4 Mb NOR flash memory technology. Sci. China Inf. Sci. 57(6): 1-9 (2014)
• 
  Shengbo Zhang, Jun Xiao, Guangjun Yang, Jian Hu, Mingyong Huang, Shichang Zou:
  A 1.35-V 16-Mb Twin-Bit-Cell Virtual-Ground-Architecture Embedded Flash Memory With a Sensing Current Protection Technique. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(10): 2862-2868 (2014)
• 
  Evaldo Carlos Fonseca Pereira, Odair Lelis Goncalez, Rafael Galhardo Vaz, Claudio Antonio Federico, Thiago Hanna Both, Gilson Inácio Wirth:
  The effects of total ionizing dose on the neutron SEU cross section of a 130 nm 4 Mb SRAM memory. LATW 2014: 1-4
• 2013
• 
  Peter Gillingham, David Chinn, Eric Choi, Jin-Ki Kim, Don MacDonald, Hakjune Oh, Hong-Beom Pyeon, Roland Schuetz:
  800 MB/s DDR NAND Flash Memory Multi-Chip Package With Source-Synchronous Interface for Point-to-Point Ring Topology. IEEE Access 1: 811-816 (2013)
• 2012
• 
  Chulbum Kim, Jinho Ryu, Tae-Sung Lee, Hyunggon Kim, Jaewoo Lim, Jaeyong Jeong, Seonghwan Seo, Hongsoo Jeon, Bokeun Kim, Inyoul Lee, Dooseop Lee, Pansuk Kwak, Seongsoon Cho, Yongsik Yim, Changhyun Cho, Woopyo Jeong, Kwang-Il Park, Jin-Man Han, Duheon Song, Kyehyun Kyung, Youngho Lim, Young-Hyun Jun:
  A 21 nm High Performance 64 Gb MLC NAND Flash Memory With 400 MB/s Asynchronous Toggle DDR Interface. IEEE J. Solid State Circuits 47(4): 981-989 (2012)
• 2011
• 
  Michaël Pelissier, Joni Jantunen, Bertrand Gomez, Jarmo Arponen, Gilles Masson, Serigne Dia, Jaakko Varteva, Marjorie Gary:
  A 112 Mb/s Full Duplex Remotely-Powered Impulse-UWB RFID Transceiver for Wireless NV-Memory Applications. IEEE J. Solid State Circuits 46(4): 916-927 (2011)
• 
  Guido De Sandre, Luca Bettini, Alessandro Pirola, Lionel Marmonier, Marco Pasotti, Massimo Borghi, Paolo Mattavelli, Paola Zuliani, Luca Scotti, Gianfranco Mastracchio, Ferdinando Bedeschi, Roberto Gastaldi, Roberto Bez:
  A 4 Mb LV MOS-Selected Embedded Phase Change Memory in 90 nm Standard CMOS Technology. IEEE J. Solid State Circuits 46(1): 52-63 (2011)
• 
  Hongwei Hong, Zheng Li, Qin Li, Ruizhe Wang, Charlie Hwang:
  A 90 nm 16 Mb embedded phase-change memory macro with write current smoothing and enhanced write bandwidth. ASICON 2011: 315-318
• 2010
• 
  Riichiro Takemura, Takayuki Kawahara, Katsuya Miura, Hiroyuki Yamamoto, Jun Hayakawa, Nozomu Matsuzaki, Kazuo Ono, Michihiko Yamanouchi, Kenchi Ito, Hiromasa Takahashi, Shoji Ikeda, Haruhiro Hasegawa, Hideyuki Matsuoka, Hideo Ohno:
  A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and '1'/'0' Dual-Array Equalized Reference Scheme. IEEE J. Solid State Circuits 45(4): 869-879 (2010)
• 2009
• 
  Yan Li, Seungpil Lee, Yupin Fong, Feng Pan, Tien-Chien Kuo, Jongmin Park, Tapan Samaddar, Hao Nguyen, Man Mui, Khin Htoo, Teruhiko Kamei, Masaaki Higashitani, Emilio Yero, Gyuwan Kwon, Phil Kliza, Jun Wan, Tetsuya Kaneko, Hiroshi Maejima, Hitoshi Shiga, Makoto Hamada, Norihiro Fujita, Kazunori Kanebako, Eugene Tam, Anne Koh, Iris Lu, Calvin Chia-Hong Kuo, Trung Pham, Jonathan Huynh, Qui Nguyen, Hardwell Chibvongodze, Mitsuyuki Watanabe, Ken Oowada, Grishma Shah, Byungki Woo, Ray Gao, Jim Chan, James Lan, Patrick Hong, Liping Peng, Debi Das, Dhritiman Ghosh, Vivek Kalluru, Sanjay Kulkarni, Raul-Adrian Cernea, Sharon Huynh, Dimitris Pantelakis, Chi-Ming Wang, Khandker Quader:
  A 16 Gb 3-Bit Per Cell (X3) NAND Flash Memory on 56 nm Technology With 8 MB/s Write Rate. IEEE J. Solid State Circuits 44(1): 195-207 (2009)
• 
  Dinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah, Jason Howard, Gregory Ruhl, Tanay Karnik, Shekhar Borkar, Vivek K. De, Ali Keshavarzi:
  2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology. IEEE J. Solid State Circuits 44(1): 174-185 (2009)
• 
  Tyler L. Brandon, John C. Koob, Leendert van den Berg, Zhengang Chen, Amirhossein Alimohammad, Ramkrishna Swamy, Jason Klaus, Stephen Bates, Vincent C. Gaudet, Bruce F. Cockburn, Duncan G. Elliott:
  A Compact 1.1-Gb/s Encoder and a Memory-Based 600-Mb/s Decoder for LDPC Convolutional Codes. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(5): 1017-1029 (2009)
• 2008
• 
  Jung-Sik Kim, Kyung-Woo Nam, Chi Sung Oh, Han Gu Sohn, Donghyuk Lee, Sooyoung Kim, Jong-Wook Park, Yongjun Kim, Mi-Jo Kim, Jin-Guk Kim, Hocheol Lee, Jinhyoung Kwon, Dong Il Seo, Young-Hyun Jun, Kinam Kim:
  A 512 Mb Two-Channel Mobile DRAM (OneDRAM) With Shared Memory Array. IEEE J. Solid State Circuits 43(11): 2381-2389 (2008)
• 
  Guido De Sandre, Luca Bettini, Emanuela Calvetti, G. Giacomi, Marco Pasotti, Massimo Borghi, Paola Zuliani, R. Annunziata, I. Tortorelli, Fabio Pellizzer, Roberto Bez:
  Program circuit for a phase change memory array with 2 MB/s write throughput for embedded applications. ESSCIRC 2008: 198-201
• 2007
• 
  Sangbeom Kang, Woo-Yeong Cho, Beak-Hyung Cho, KwangJin Lee, Changsoo Lee, Hyung-Rok Oh, Byung-Gil Choi, Qi Wang, Hye-Jin Kim, Mu-Hui Park, Yu-Hwan Ro, Suyeon Kim, Choong-Duk Ha, Ki-Sung Kim, Young-Ran Kim, Du-Eung Kim, Choong-Keun Kwak, Hyun-Geun Byun, Gitae Jeong, Hong-Sik Jeong, Kinam Kim, YunSueng Shin:
  A 0.1-µm 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation. IEEE J. Solid State Circuits 42(1): 210-218 (2007)
• 
  Ken Takeuchi, Yasushi Kameda, Susumu Fujimura, Hiroyuki Otake, Koji Hosono, Hitoshi Shiga, Yoshihisa Watanabe, Takuya Futatsuyama, Yoshihiko Shindo, Masatsugu Kojima, Makoto Iwai, Masanobu Shirakawa, Masayuki Ichige, Kazuo Hatakeyama, Shinichi Tanaka, Teruhiko Kamei, Jia-Yi Fu, Adi Cernea, Yan Li, Masaaki Higashitani, Gertjan Hemink, Shinji Sato, Ken Oowada, Shih-Chung Lee, Naoki Hayashida, Jun Wan, Jeffrey Lutze, Shouchang Tsao, Mehrdad Mofidi, Kiyofumi Sakurai, Naoya Tokiwa, Hiroko Waki, Yasumitsu Nozawa, Kazuhisa Kanazawa, Shigeo Ohshima:
  A 56-nm CMOS 99-mm² 8-Gb Multi-Level NAND Flash Memory With 10-MB/s Program Throughput. IEEE J. Solid State Circuits 42(1): 219-232 (2007)
• 
  Adrian Petcu, Boi Faltings:
  MB-DPOP: A New Memory-Bounded Algorithm for Distributed Optimization. IJCAI 2007: 1452-1457
• 2006
• 
  Hideaki Kurata, Shunichi Saeki, Takashi Kobayashi, Yoshitaka Sasago, Tsuyoshi Arigane, Keiichi Yoshida, Yoshinori Takase, Takayuki Yoshitake, Osamu Tsuchiya, Yoshinori Ikeda, Shunichi Narumi, Michitaro Kanamitsu, Kazuto Izawa, Kazunori Furusawa:
  A 130-nm CMOS 95-mm² 1-Gb Multilevel AG-AND-Type Flash Memory with 10-MB/s Programming Throughput. IEICE Trans. Electron. 89-C(10): 1469-1479 (2006)