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Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.
found 4 matches
- Leonidas Kosmidis, Charlie Curtsinger, Eduardo Quiñones, Jaume Abella, Emery D. Berger, Francisco J. Cazorla:
Probabilistic timing analysis on conventional cache designs. DATE 2013: 603-606
- Ryusuke Egawa, Jubee Tada, Yusuke Endo, Hiroyuki Takizawa, Hiroaki Kobayashi:
Poster: Exploring Design Space of a 3D Stacked Vector Cache - Designing a 3D Stacked Vector Cache using Conventional EDA Tools. SC Companion 2012: 1477
- Gabriel H. Loh, Mark D. Hill:
Efficiently enabling conventional block sizes for very large die-stacked DRAM caches. MICRO 2011: 454-464
- Ekachai Leelarasmee, Methee Hwangkhunnatham:
An Implementation of a Matrix Cache to Speed up the Conventional Transient Simulation of Piecewise Linear Circuits. J. Circuits Syst. Comput. 7(4): 353-360 (1997)
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