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found 7 matches
- Sarang Kazeminia, Maryam Ghafoorzadeh, Faeze Noruzpur:
An extendable global clock high-speed binary counter compatible to the FPGA CLBs. MIXDES 2017: 220-223
- Arwa Ben Dhia, Lirida A. B. Naviner, Philippe Matherat:
Comparison of fault-tolerant fabless CLBs in SRAM-based FPGAs. LATW 2013: 1-6
- Yong Fu, Chi Wang, Liguang Chen, Jinmei Lai:
A novel full coverage test method for CLBs in FPGA (abstract only). FPGA 2012: 267
- Arwa Ben Dhia, Lirida Alves de Barros Naviner, Philippe Matherat:
A new fault-tolerant architecture for CLBs in SRAM-based FPGAs. ICECS 2012: 761-764
- Anjela Yu. Matrosova, Ekaterina Loukovnikova, Sergei Ostanin, Alexandra Zinchuk, Ekaterina Nikolaeva:
Test Generation for Single and Multiple Stuck-at Faults of a Combinational Circuit Designed by Covering Shared ROBDD with CLBs. DFT 2007: 206-214
- Nadia Nedjah, Luiza de Macedo Mourelle:
How Many CLBs Does Your Circuit Need to be Implemented?. IEEE International Workshop on Rapid System Prototyping 2001: 174-181
- G. Bozikian, J. William Atwood:
CICS LSR Buffer Simulator (CLBS). Int. CMG Conference 1988: 493-503
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