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Wing-Kai Chow , Jian Kuang , Peishan Tu , Evangeline F. Y. Young : Fence-aware detailed-routability driven placement. SLIP 2017 : 1-7 share record
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Isuru Daulagala , Ioannis Savidis : Clock tree synthesis for heterogeneous 3-D integrated circuits. SLIP 2017 : 1-6 share record
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Leo Filippini , Baris Taskin : A charge recovery logic system bus. SLIP 2017 : 1-4 share record
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Jinglei Huang , Xiaodong Xu , Lan Yao , Song Chen : Reconfigurable topology synthesis for application-specific noc on partially dynamically reconfigurable FPGAs. SLIP 2017 : 1-8 share record
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Scott Lerner , Eric Leggett , Baris Taskin : Slew-down: analysis of slew relaxation for low-impact clock buffers. SLIP 2017 : 1-4 share record
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Ulf Schlichtmann : Frontiers of timing. SLIP 2017 : 1-4 share record
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Peishan Tu , Wing-Kai Chow , Evangeline F. Y. Young : Timing driven routing tree construction. SLIP 2017 : 1-8 share record
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ACM/IEEE 2017 International Workshop on System Level Interconnect Prediction, SLIP 2017, Austin, TX, USA, June 17, 2017. IEEE Computer Society 2017 , ISBN 978-1-5386-1536-2 [contents] 2016 share record
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Mohammad A. Ahmed , Sucheta Mohapatra , Malgorzata Chrzanowska-Jeske : Buffered Interconnects in 3D IC Layout Design. SLIP 2016 : 4:1-4:8 share record
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Roman P. Bazylevych , Marek Palasinski , Lubov Bazylevych : Topologically-Geometric Routing. SLIP 2016 : 5:1-5:6 share record
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Wei-Ting Jonas Chan , Andrew B. Kahng , Jiajia Li : Revisiting 3DIC Benefit with Multiple Tiers. SLIP 2016 : 6:1-6:8 share record
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Enes Eken , Ismail Bayram , Yaojun Zhang , Bonan Yan , Wenqing Wu , Hai (Helen) Li , Yiran Chen : Spin-Hall Assisted STT-RAM Design and Discussion. SLIP 2016 : 7:1-7:4 share record
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Chih-Cheng Hsu , Mark Po-Hung Lin , Masanori Hashimoto : Latch Clustering for Minimizing Detection-to-Boosting Latency Toward Low-Power Resilient Circuits. SLIP 2016 : 2:1-2:6 share record
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Naseef Mansoor , Md Shahriar Shamim , Amlan Ganguly : A Demand-Aware Predictive Dynamic Bandwidth Allocation Mechanism for Wireless Network-on-Chip. SLIP 2016 : 8:1-8:8 share record
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Carrie Segal , Aditya Dalakoti , Merritt Miller , Forrest Brewer : Connectivity Effects on Energy and Area for Neuromorphic System with High Speed Asynchronous Pulse Mode Links. SLIP 2016 : 3:1-3:7 share record
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Ishan G. Thakkar , Sai Vineel Reddy Chittamuru , Sudeep Pasricha : A Comparative Analysis of Front-End and Back-End Compatible Silicon Photonic On-Chip Interconnects. SLIP 2016 : 1:1-1:8 share record
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Baris Taskin , Tsung-Yi Ho : Proceedings of the 18th System Level Interconnect Prediction Workshop, SLIP 2016, Austin, TX, USA, June 4, 2016. ACM 2016 , ISBN 978-1-4503-4430-2 [contents] 2015 share record
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Samyoung Bang , Kwangsoo Han , Andrew B. Kahng , Vaishnav Srinivas : Clock clustering and IO optimization for 3D integration. SLIP 2015 : 1-8 share record
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Sai Manoj P. D. , Kanwen Wang , Hantao Huang , Hao Yu : Smart I/Os: a data-pattern aware 2.5D interconnect with space-time multiplexing. SLIP 2015 : 1-6 export record
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conf/slip/EscalanteKKOS15 share record
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Marco Escalante , Andrew B. Kahng , Michael Kishinevsky , Ümit Y. Ogras , Kambiz Samadi : Multi-product floorplan and uncore design framework for chip multiprocessors. SLIP 2015 : 1-7 share record
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Tsung-Wei Huang , Martin D. F. Wong : On fast timing closure: speeding up incremental path-based timing analysis with mapreduce. SLIP 2015 : 1-6 share record
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Andrew B. Kahng , Mulong Luo , Siddhartha Nath : SI for free: machine learning of interconnect coupling delay and transition effects. SLIP 2015 : 1-8 share record
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Rui Wu , Chin-Hui Chen , Jean-Marc Fedeli , Maryse Fournier , Raymond G. Beausoleil , Kwang-Ting Cheng : Compact modeling and system implications of microring modulators in nanophotonic interconnects. SLIP 2015 : 1-6 share record
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Haifeng Xu , Melissa M. Bilec , William O. Collinge , Laura A. Schaefer , Amy E. Landis , Alex K. Jones : Lynx: a self-organizing wireless sensor network with commodity palmtop computers. SLIP 2015 : 1-7 share record
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Xiang Zhang , Yang Liu , Ryan Coutts , Chung-Kuan Cheng : Power line communication for hybrid power/signal pin SOC design. SLIP 2015 : 1-8 share record
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2015 ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2015, San Francisco, CA, USA, June 6, 2015. IEEE Computer Society 2015 , ISBN 978-1-4673-8189-5 [contents] 2014 share record
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Wei-Ting Jonas Chan , Andrew B. Kahng , Siddhartha Nath : Methodology for electromigration signoff in the presence of adaptive voltage scaling. SLIP 2014 : 6:1-6:7 share record
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Tsung-Wei Huang , Pei-Ci Wu , Martin D. F. Wong : UI-route: An ultra-fast incremental maze routing algorithm. SLIP 2014 : 4:1-4:8 share record
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Julian Kemmerer , Baris Taskin : Range-based dynamic routing of hierarchical on chip network traffic. SLIP 2014 : 5:1-5:9 share record
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Inna Vaisband , Eby G. Friedman : Power network-on-chip for scalable power delivery. SLIP 2014 : 1:1-1:5