- Dorin Emil Calbaza, Yvon Savaria:
A direct digital period synthesis circuit. IEEE J. Solid State Circuits 37(8): 1039-1045 (2002) - Jun Cao, Michael M. Green, Afshin Momtaz, Kambiz Vakilian, David Chung, Keh-Chee Jen, Mario Caresosa, Xin Wang, Wee-Guan Tan, Yijun Cai, Ichiro Fujimori, Armond Hairapetian:
OC-192 transmitter and receiver in standard 0.18-μm CMOS. IEEE J. Solid State Circuits 37(12): 1768-1780 (2002) - Hsiang-Hui Chang, Jyh-Woei Lin, Ching-Yuan Yang, Shen-Iuan Liu:
A wide-range delay-locked loop with a fixed latency of one clock cycle. IEEE J. Solid State Circuits 37(8): 1021-1027 (2002) - Oscal T.-C. Chen, Robin Ruey-Bin Sheen:
A power-efficient wide-range phase-locked loop. IEEE J. Solid State Circuits 37(1): 51-62 (2002) - Vincent S. L. Cheung, Howard C. Luong, Wing-Hung Ki:
A 1-V 10.7-MHz switched-opamp bandpass ΣΔ modulator using double-sampling finite-gain-compensation technique. IEEE J. Solid State Circuits 37(10): 1215-1225 (2002) - Ming-Chou Chiang, Shey-Shi Lu, Chin-Chun Meng, Shih-An Yu, Shih-Cheng Yang, Yi-Jen Chan:
Analysis, design, and optimization of InGaP-GaAs HBT matched-impedance wide-band amplifiers with multiple feedback loops. IEEE J. Solid State Circuits 37(6): 694-701 (2002) - Uma Chilakapati, Terri S. Fiez, Aria Eshraghi:
A CMOS transconductor with 80-dB SFDR up to 10 MHz. IEEE J. Solid State Circuits 37(3): 365-370 (2002) - Mun-Kyu Choi, Byung-Gil Jeon, Nakwon Jang, Byung-Jun Min, Yoon-Jong Song, Sung-Yung Lee, Hyun-Ho Kim, Dong-Jin Jung, Heung-Jin Joo, Kinam Kim:
A 0.25-μm 3.0-V 1T1C 32-Mb nonvolatile ferroelectric RAM with address transition detector and current forcing latch sense amplifier scheme. IEEE J. Solid State Circuits 37(11): 1472-1478 (2002) - Shang-Yuan (Sean) Chuang, Terry L. Sculley:
A digitally self-calibrating 14-bit 10-MHz CMOS pipelined A/D converter. IEEE J. Solid State Circuits 37(6): 674-683 (2002) - Ugur Çilingiroglu, Luthuli Edem Dake:
Rank-order filter design with a sampled-analog multiple-winners-take-all core. IEEE J. Solid State Circuits 37(8): 978-984 (2002) - Danielle Coffing, Eric Main, Mark Randol, Gina Szklarz:
A variable gain amplifier with 50-dB control range for 900-MHz applications. IEEE J. Solid State Circuits 37(9): 1169-1175 (2002) - José Higino Correia, Ger de Graaf, Marian Bartek, Reinoud F. Wolffenbuttel:
A single-chip CMOS optical microspectrometer with light-to-frequency converter and bus interface. IEEE J. Solid State Circuits 37(10): 1344-1347 (2002) - Salvatore Cosentino, Pietro Filoramo, Angelo Granata, Marco Marletta, Giuseppe Martino, Roberto Pelleriti, Felice Torrisi, Mario Paparo, Gaetano Cosentino, Piero Vita, Giuseppe Palmisano:
An integrated RF transceiver for DECT application. IEEE J. Solid State Circuits 37(3): 443-449 (2002) - Jeroen A. Croon, Maarten Rosmeulen, Stefaan Decoutere, Willy Sansen, Herman E. Maes:
An easy-to-use mismatch model for the MOS transistor. IEEE J. Solid State Circuits 37(8): 1056-1064 (2002) - Nicola Da Dalt, Sven Derksen, Patrizia Greco, Christoph Sandner, Harald Schmid, Klaus Strohmayer:
A fully integrated 2.4-GHz LC-VCO frequency synthesizer with 3-ps jitter in 0.18-μm standard digital CMOS copper technology. IEEE J. Solid State Circuits 37(7): 959-962 (2002) - W. Rhett Davis, Ning Zhang, Kevin Camera, Dejan Markovic, Tina Smilkstein, M. Josie Ammer, Engling Yeo, Stephanie Augsburger, Borivoje Nikolic, Robert W. Brodersen:
A design environment for high-throughput low-power dedicated signal processing systems. IEEE J. Solid State Circuits 37(3): 420-431 (2002) - Andreas Demosthenous, John Taylor:
A 100-Mb/s 2.8-V CMOS current-mode analog Viterbi decoder. IEEE J. Solid State Circuits 37(7): 904-910 (2002) - Conor Donovan, Michael P. Flynn:
A "digital" 6-bit ADC in 0.25-μm CMOS. IEEE J. Solid State Circuits 37(3): 432-437 (2002) - Shiro Dosho, Takashi Morie, Hirokuni Fujiyama:
A 200-MHz seventh-order equiripple continuous-time filter by design of nonlinearity suppression in 0.25-μm CMOS process. IEEE J. Solid State Circuits 37(5): 559-565 (2002) - Dirk Droste, Josef Bille:
An ASIC for Hartmann-Shack wavefront detection. IEEE J. Solid State Circuits 37(2): 173-182 (2002) - Frank Ellinger, Werner Bächtold:
Novel principle for vector modulator-based phase shifters operating with only one control voltage. IEEE J. Solid State Circuits 37(10): 1256-1259 (2002) - Frank Ellinger, Rolf Vogt, Werner Bächtold:
Ultracompact reflective-type phase shifter MMIC at C-band with 360° phase-control range for smart antenna combining. IEEE J. Solid State Circuits 37(4): 481-486 (2002) - Christian C. Enz, Stefan Rusu:
Guest editorial. IEEE J. Solid State Circuits 37(7): 795-797 (2002) - Amr M. Fahim, Mohamed I. Elmasry:
Low-power high-performance arithmetic circuits and architectures. IEEE J. Solid State Circuits 37(1): 90-94 (2002) - Ramin Farjad-Rad, William J. Dally, Hiok-Tiaq Ng, Ramesh Senthinathan, Ming-Ju Edward Lee, Rohit Rathi, John Poulton:
A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips. IEEE J. Solid State Circuits 37(12): 1804-1812 (2002) - Eric S. Fetzer, Mark Gibson, Anthony Klein, Naomi Calick, Chengyu Zhu, Eric Busta, Baker Mohammad:
A fully bypassed six-issue integer datapath and register file on the Itanium-2 microprocessor. IEEE J. Solid State Circuits 37(11): 1433-1440 (2002) - Brian A. Floyd, Chih-Ming Hung, Kenneth K. O:
Intra-chip wireless interconnect for clock distribution implemented with integrated antennas, receivers, and transmitters. IEEE J. Solid State Circuits 37(5): 543-552 (2002) - David J. Foley, Michael P. Flynn:
A low-power 8-PAM serial transceiver in 0.5-μm digital CMOS. IEEE J. Solid State Circuits 37(3): 310-316 (2002) - Douglas J. Fouts, Phillip E. Pace, Christopher Karow, Stig R. T. Ekestorm:
A single-chip false target radar image generator for countering wideband imaging radars. IEEE J. Solid State Circuits 37(6): 751-759 (2002) - Robert M. Fox, R. Chawla, William R. Eisenstadt, D. Hemmenway, J. Johnston:
Circuit for monitoring BJT RF performance using DC measurements. IEEE J. Solid State Circuits 37(9): 1207-1210 (2002)