- Casey Reardon, Alan D. George, Greg Stitt, Herman Lam:
An Automated Scheduling and Partitioning Algorithm for Scalable Reconfigurable Computing Systems. ERSA 2010: 187-193 - Daisaku Seto, Minoru Watanabe:
Partial Block-by-Block Reconfiguration for a Dynamic Optically Reconfigurable Gate Array. ERSA 2010: 232-237 - Eric Stahlberg:
Standards for Sustainability - Growing Markets and Improving Access for Reconfigurable Supercomputing. ERSA 2010: 121-126 - Russell Tessier, Salma Mirza, J. Blair Perot:
Reconfigurable Sparse Matrix-Vector Multiplication on FPGAs. ERSA 2010: 77-83 - Lionel Torres, Yoann Guillemenet, Syed Zahid Ahmed:
A Dynamic Reconfigurable MRAM based FPGA. ERSA 2010: 31-40 - Pranav Vaidya, Yu Chen, Jaehwan John Lee, Chandima H. Nadungodage, Yuni Xia:
A General Purpose FPGA Data Filter for Data Stream Processing. ERSA 2010: 247-250 - Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama:
Architecture of an FPGA-Oriented Heterogeneous Multi-core Processor with SIMD-Accelerator Cores. ERSA 2010: 179-186 - Hasitha Muthumala Waidyasooriya, Daisuke Okumura, Masanori Hariyama, Michitaka Kameyama:
Mapping for a Heterogeneous Multi-Core Media Processor Considering the Data Transfer Time. ERSA 2010: 281-284 - Akira Yamawaki, Seiichi Serikawa:
An Architecture of Prototyping System for Dynamic Partial Reconfiguration on FPGA. ERSA 2010: 263-266 - Shaon Yousuf, Ann Gordon-Ross:
DAPR: Design Automation for Partially Reconfigurable FPGAs. ERSA 2010: 97-103 - Ali Akbar Zarezadeh, Christophe Bobda:
Hardware ORB Middleware for Distributed Smart Camera Systems. ERSA 2010: 104-116 - Toomas P. Plaks, David Andrews, Ronald F. DeMara, Herman Lam, Jooheung Lee, Christian Plessl, Greg Stitt:
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA 2010, July 12-15, 2010, Las Vegas Nevada, USA. CSREA Press 2010, ISBN 1-60132-140-6 [contents] - 2009
- Andrea Abba, Antonio Manenti, Andrea Suardi, Angelo Geraci, Giancarlo Ripamonti:
Implementation of the Gauss-Newton Algorithm for Non-linear Least-mean-squares Fitting in FPGA Devices. ERSA 2009: 240-246 - Hideharu Amano:
Japanese Dynamically Reconfigurable Processors. ERSA 2009: 19-28 - Peter Athanas:
Element CXI: Exploring Element Computing in Academia. ERSA 2009: 101 - Jürgen Becker:
Adaptive Multicore Systems-on-Chip (MSoC) - Design and Computing in the Nano Era. ERSA 2009: 55-66 - Abderrahmane Bennis, Miriam Leeser, Gilead Tadmor:
The Effect of Parameterization on a Reconfigurable Implementation of PIV. ERSA 2009: 105-111 - Ray Bittner:
The Speedy DDR2 Controller For FPGAs. ERSA 2009: 205-211 - Luigi Carro, Monica Magalhães Pereira:
Adaptive Processing Architectures for the Ultimate Scaling of the CMOS World. ERSA 2009: 91-97 - Guojun Dai, Peng Liu, Y. Fun Hu, Geyong Min, Zhigang Gao:
Transformable Vertexes Information based Algorithm for Online Task Placement in Reconfigurable System. ERSA 2009: 279-282 - Jean-Philippe Diguet, Linfeng Ye, Yvan Eustache, Jérémie Crenne, Pierre Bomel, Guy Gogniat, Jorgiano Vidal, Florent de Lamotte:
Networked Self-adaptive Systems: An Opportunity for Configuring in the Large. ERSA 2009: 81-90 - Qian Ding, William Robinson:
An FPGA Implementation of an Elliptic Curve Cryptosystem Coprocessor over Prime Fields. ERSA 2009: 303-304 - Hassan Edrees, Brian Cheung, McCullen Sandora, David B. Nummey, Deian Stefan:
Hardware-Optimized Ziggurat Algorithm for High-Speed Gaussian Random Number Generators. ERSA 2009: 254-260 - Mahmood Fazlali, Ali Zakerolhosseini, Mojtaba Sabeghi, Koen Bertels, Georgi Gaydadjiev:
Data path Configuration Time Reduction for Run-time Reconfigurable Systems. ERSA 2009: 323-327 - Mariusz Grad, Christian Plessl:
Woolcano: An Architecture And Tool Flow For Dynamic Instruction Set Extension On Xilinx Virtex-4 FX. ERSA 2009: 319-322 - Paolo Roberto Grassi, Marco D. Santambrogio, Jens Hagemeyer, Christopher Pohl, Mario Porrmann:
SiLLis: A Simplified Language for Monitoring and Debugging of Reconfigurable Systems. ERSA 2009: 174-180 - Masanori Hariyama, Keita Tanji, Michitaka Kameyama:
FPGA Implementation of a High-Speed Stereo Matching Processor Based on Recursive Computation. ERSA 2009: 263-266 - Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama:
A Fine-Grain SIMD Architecture Based on Flexible Ferroelectric-Capacitor Logic. ERSA 2009: 271-274 - Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama:
An Asynchronous Field-Programmable VLSI Using LEDR/4-Phase-Dual-Rail Protocol Converters. ERSA 2009: 145-150 - Christophe Jégo:
FPGA Prototyping Approach for the Validation of Efficient Iterative Decoders in Digital Communication Systems. ERSA 2009: 9-18