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@article{DBLP:journals/vlsisp/BhattacharyyaML99,
  author       = {Shuvra S. Bhattacharyya and
                  Praveen K. Murthy and
                  Edward A. Lee},
  title        = {Synthesis of Embedded Software from Synchronous Dataflow Specifications},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {21},
  number       = {2},
  pages        = {151--166},
  year         = {1999},
  url          = {https://doi.org/10.1023/A:1008052406396},
  doi          = {10.1023/A:1008052406396},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/BhattacharyyaML99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/BossungHK99,
  author       = {Wolfgang Bo{\ss}ung and
                  Sorin Alexander Huss and
                  Stephan Klaus},
  title        = {High-Level Embedded System Specifications Based on Process Activation
                  Conditions},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {21},
  number       = {3},
  pages        = {277--291},
  year         = {1999},
  url          = {https://doi.org/10.1023/A:1008191425265},
  doi          = {10.1023/A:1008191425265},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/BossungHK99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/Catthoor99,
  author       = {Francky Catthoor},
  title        = {Energy-Delay Efficient Data Storage and Transfer Architectures and
                  Methodologies: Current Solutions and Remaining Problems},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {21},
  number       = {3},
  pages        = {219--231},
  year         = {1999},
  url          = {https://doi.org/10.1023/A:1008181319813},
  doi          = {10.1023/A:1008181319813},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/Catthoor99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/DoughertyPT99,
  author       = {William E. Dougherty and
                  David J. Pursley and
                  Donald E. Thomas},
  title        = {Subsetting Behavioral Intellectual Property for Low Power {ASIP} Design},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {21},
  number       = {3},
  pages        = {209--218},
  year         = {1999},
  url          = {https://doi.org/10.1023/A:1008010602067},
  doi          = {10.1023/A:1008010602067},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/DoughertyPT99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/HeT99,
  author       = {Shousheng He and
                  Mats Torkelson},
  title        = {An Orthogonal Time-Frequency Extraction Approach to 2D Systolic Architecture
                  for 1D {DFT} Computation},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {21},
  number       = {1},
  pages        = {61--70},
  year         = {1999},
  url          = {https://doi.org/10.1023/A:1008027706032},
  doi          = {10.1023/A:1008027706032},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/HeT99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/HsiehM99,
  author       = {Jeff Y. F. Hsieh and
                  Teresa H.{-}Y. Meng},
  title        = {Low-Power Parallel Video Compression Architecture for a Single-Chip
                  Digital {CMOS} Camera},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {21},
  number       = {3},
  pages        = {195--207},
  year         = {1999},
  url          = {https://doi.org/10.1023/A:1008006400249},
  doi          = {10.1023/A:1008006400249},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/HsiehM99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/KiviojaIV99,
  author       = {M. Kivioja and
                  Jouni Isoaho and
                  L. V{\"{a}}nsk{\"{a}}},
  title        = {Design and Implementation of Viterbi Decoder with FPGAs},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {21},
  number       = {1},
  pages        = {5--14},
  year         = {1999},
  url          = {https://doi.org/10.1023/A:1008067404215},
  doi          = {10.1023/A:1008067404215},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/KiviojaIV99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/KwaiP99,
  author       = {Ding{-}Ming Kwai and
                  Behrooz Parhami},
  title        = {Scalability of Programmable {FIR} Digital Filters},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {21},
  number       = {1},
  pages        = {31--35},
  year         = {1999},
  url          = {https://doi.org/10.1023/A:1008023605124},
  doi          = {10.1023/A:1008023605124},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/KwaiP99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/MukherjeeF99,
  author       = {Tamal Mukherjee and
                  Gary K. Fedder},
  title        = {Hierarchical Mixed-Domain Circuit Simulation, Synthesis and Extraction
                  Methodology for {MEMS}},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {21},
  number       = {3},
  pages        = {233--249},
  year         = {1999},
  url          = {https://doi.org/10.1023/A:1008122921631},
  doi          = {10.1023/A:1008122921631},
  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/MukherjeeF99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/NegoiBZG99,
  author       = {Andy Negoi and
                  Stefan Bara and
                  Jacques Zimmermann and
                  Alain Guyot},
  title        = {A Dedicated Circuit for Charged Particles Simulation Using the Monte
                  Carlo Method},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {21},
  number       = {2},
  pages        = {103--116},
  year         = {1999},
  url          = {https://doi.org/10.1023/A:1008096121417},
  doi          = {10.1023/A:1008096121417},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/NegoiBZG99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/RiederSS99,
  author       = {Peter Rieder and
                  Sven Simon and
                  Christian V. Schimpfle},
  title        = {Application Specific Efficient {VLSI} Architectures for Orthogonal
                  Single- and Multiwavelet Transforms},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {21},
  number       = {2},
  pages        = {77--90},
  year         = {1999},
  url          = {https://doi.org/10.1023/A:1008092020509},
  doi          = {10.1023/A:1008092020509},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/RiederSS99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/SanchezLPTZ99,
  author       = {Manuel S{\'{a}}nchez and
                  Juan L{\'{o}}pez and
                  Oscar G. Plata and
                  Mar{\'{\i}}a A. Trenas and
                  Emilio L. Zapata},
  title        = {An Efficient Architecture for the In-Place Fast Cosine Transform},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {21},
  number       = {2},
  pages        = {91--102},
  year         = {1999},
  url          = {https://doi.org/10.1023/A:1008044104579},
  doi          = {10.1023/A:1008044104579},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/SanchezLPTZ99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/SmailagicM99,
  author       = {Asim Smailagic and
                  Hugo De Man},
  title        = {Guest Editors' Introduction},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {21},
  number       = {3},
  pages        = {183--184},
  year         = {1999},
  url          = {https://doi.org/10.1023/A:1008046131200},
  doi          = {10.1023/A:1008046131200},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/SmailagicM99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/SmailagicS99,
  author       = {Asim Smailagic and
                  Daniel P. Siewiorek},
  title        = {System Level Design as Applied to {CMU} Wearable Computers},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {21},
  number       = {3},
  pages        = {251--263},
  year         = {1999},
  url          = {https://doi.org/10.1023/A:1008131106610},
  doi          = {10.1023/A:1008131106610},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/SmailagicS99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/SrinivasP99,
  author       = {Hosahalli R. Srinivas and
                  Keshab K. Parhi},
  title        = {A Radix 2 Shared Division/Square Root Algorithm and its {VLSI} Architecture},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {21},
  number       = {1},
  pages        = {37--60},
  year         = {1999},
  url          = {https://doi.org/10.1023/A:1008075621962},
  doi          = {10.1023/A:1008075621962},
  timestamp    = {Tue, 07 May 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/SrinivasP99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/StineS99,
  author       = {James E. Stine and
                  Michael J. Schulte},
  title        = {The Symmetric Table Addition Method for Accurate Function Approximation},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {21},
  number       = {2},
  pages        = {167--177},
  year         = {1999},
  url          = {https://doi.org/10.1023/A:1008004523235},
  doi          = {10.1023/A:1008004523235},
  timestamp    = {Sat, 05 Sep 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/StineS99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/Taylor99,
  author       = {Valerie E. Taylor},
  title        = {Guest Editor's Introduction},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {21},
  number       = {2},
  pages        = {75},
  year         = {1999},
  url          = {https://doi.org/10.1023/A:1008037103670},
  doi          = {10.1023/A:1008037103670},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/Taylor99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/VerkestSYCMWCJM99,
  author       = {Diederik Verkest and
                  Julio Leao da Silva Jr. and
                  Chantal Ykman{-}Couvreur and
                  Kris Croes and
                  Miguel Miranda and
                  Sven Wuytack and
                  Francky Catthoor and
                  Gjalt G. de Jong and
                  Hugo De Man},
  title        = {Matisse: {A} System-on-Chip Design Methodology Emphasizing Dynamic
                  Memory Management},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {21},
  number       = {3},
  pages        = {185--194},
  year         = {1999},
  url          = {https://doi.org/10.1023/A:1008002332109},
  doi          = {10.1023/A:1008002332109},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/VerkestSYCMWCJM99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/WahW99,
  author       = {Benjamin W. Wah and
                  Zhe Wu},
  title        = {Discrete Lagrangian Methods for Designing Multiplierless Two-Channel
                  {PR-LP} Filter Banks},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {21},
  number       = {2},
  pages        = {131--149},
  year         = {1999},
  url          = {https://doi.org/10.1023/A:1008000422326},
  doi          = {10.1023/A:1008000422326},
  timestamp    = {Fri, 19 Jan 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsisp/WahW99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/YoonHBCS99,
  author       = {Heebyung Yoon and
                  Junwei Hou and
                  Swapan K. Bhattacharya and
                  Abhijit Chatterjee and
                  Madhavan Swaminathan},
  title        = {Fault Detection and Automated Fault Diagnosis for Embedded Integrated
                  Electrical Passives},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {21},
  number       = {3},
  pages        = {265--276},
  year         = {1999},
  url          = {https://doi.org/10.1023/A:1008187207518},
  doi          = {10.1023/A:1008187207518},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/YoonHBCS99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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