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@article{DBLP:journals/ijrc/AsgharIAAPR17,
  author       = {Ali Asghar and
                  Muhammad Mazher Iqbal and
                  Waqar Ahmed and
                  Mujahid Ali and
                  Husain Parvez and
                  Muhammad Rashid},
  title        = {Exploring Shared {SRAM} Tables in FPGAs for Larger LUTs and Higher
                  Degree of Sharing},
  journal      = {Int. J. Reconfigurable Comput.},
  volume       = {2017},
  pages        = {7021056:1--7021056:9},
  year         = {2017},
  url          = {https://doi.org/10.1155/2017/7021056},
  doi          = {10.1155/2017/7021056},
  timestamp    = {Mon, 26 Jun 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ijrc/AsgharIAAPR17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ijrc/GaoALC17,
  author       = {Shuli Gao and
                  Dhamin Al{-}Khalili and
                  J. M. Pierre Langlois and
                  Noureddine Chabini},
  title        = {Efficient Realization of {BCD} Multipliers Using FPGAs},
  journal      = {Int. J. Reconfigurable Comput.},
  volume       = {2017},
  pages        = {2410408:1--2410408:12},
  year         = {2017},
  url          = {https://doi.org/10.1155/2017/2410408},
  doi          = {10.1155/2017/2410408},
  timestamp    = {Thu, 02 Apr 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ijrc/GaoALC17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ijrc/KurdiGA17,
  author       = {Aous H. Kurdi and
                  Janos L. Grantner and
                  Ikhlas Abdel{-}Qader},
  title        = {Fuzzy Logic Based Hardware Accelerator with Partially Reconfigurable
                  Defuzzification Stage for Image Edge Detection},
  journal      = {Int. J. Reconfigurable Comput.},
  volume       = {2017},
  pages        = {1325493:1--1325493:13},
  year         = {2017},
  url          = {https://doi.org/10.1155/2017/1325493},
  doi          = {10.1155/2017/1325493},
  timestamp    = {Thu, 02 Apr 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ijrc/KurdiGA17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ijrc/MhaskeKLAS17,
  author       = {Swapnil Mhaske and
                  Hojin Kee and
                  Tai Ly and
                  Ahsan Aziz and
                  Predrag Spasojevic},
  title        = {FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level
                  Synthesis},
  journal      = {Int. J. Reconfigurable Comput.},
  volume       = {2017},
  pages        = {3689308:1--3689308:23},
  year         = {2017},
  url          = {https://doi.org/10.1155/2017/3689308},
  doi          = {10.1155/2017/3689308},
  timestamp    = {Thu, 02 Apr 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ijrc/MhaskeKLAS17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ijrc/Ochoa-RuizBLDB17,
  author       = {Gilberto Ochoa{-}Ruiz and
                  Romain Bevan and
                  Florent de Lamotte and
                  Jean{-}Philippe Diguet and
                  Cheng{-}Cong Bao},
  title        = {Real-Time Control System for Improved Precision and Throughput in
                  an Ultrafast Carbon Fiber Placement Robot Using a SoC {FPGA} Extended
                  Processing Platform},
  journal      = {Int. J. Reconfigurable Comput.},
  volume       = {2017},
  pages        = {3298734:1--3298734:20},
  year         = {2017},
  url          = {https://doi.org/10.1155/2017/3298734},
  doi          = {10.1155/2017/3298734},
  timestamp    = {Thu, 02 Apr 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ijrc/Ochoa-RuizBLDB17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ijrc/TsoeunyaneWI17,
  author       = {Lekhobola Tsoeunyane and
                  Simon Winberg and
                  Michael Inggs},
  title        = {Software-Defined Radio {FPGA} Cores: Building towards a Domain-Specific
                  Language},
  journal      = {Int. J. Reconfigurable Comput.},
  volume       = {2017},
  pages        = {3925961:1--3925961:28},
  year         = {2017},
  url          = {https://doi.org/10.1155/2017/3925961},
  doi          = {10.1155/2017/3925961},
  timestamp    = {Thu, 02 Apr 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ijrc/TsoeunyaneWI17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ijrc/Venkatakrishnan17,
  author       = {Satheesh Bojja Venkatakrishnan and
                  Elias A. Alwan and
                  John L. Volakis},
  title        = {Challenges in Clock Synchronization for On-Site Coding Digital Beamformer},
  journal      = {Int. J. Reconfigurable Comput.},
  volume       = {2017},
  pages        = {7802735:1--7802735:8},
  year         = {2017},
  url          = {https://doi.org/10.1155/2017/7802735},
  doi          = {10.1155/2017/7802735},
  timestamp    = {Sun, 25 Jul 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ijrc/Venkatakrishnan17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ijrc/WaidyasooriyaEH17,
  author       = {Hasitha Muthumala Waidyasooriya and
                  Tsukasa Endo and
                  Masanori Hariyama and
                  Yasuo Ohtera},
  title        = {OpenCL-Based {FPGA} Accelerator for 3D {FDTD} with Periodic and Absorbing
                  Boundary Conditions},
  journal      = {Int. J. Reconfigurable Comput.},
  volume       = {2017},
  pages        = {6817674:1--6817674:11},
  year         = {2017},
  url          = {https://doi.org/10.1155/2017/6817674},
  doi          = {10.1155/2017/6817674},
  timestamp    = {Thu, 02 Apr 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ijrc/WaidyasooriyaEH17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ijrc/WilsonSS17,
  author       = {David Wilson and
                  Aniruddha Shastri and
                  Greg Stitt},
  title        = {A High-Level Synthesis Scheduling and Binding Heuristic for {FPGA}
                  Fault Tolerance},
  journal      = {Int. J. Reconfigurable Comput.},
  volume       = {2017},
  pages        = {5419767:1--5419767:17},
  year         = {2017},
  url          = {https://doi.org/10.1155/2017/5419767},
  doi          = {10.1155/2017/5419767},
  timestamp    = {Thu, 02 Apr 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ijrc/WilsonSS17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}