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@article{DBLP:journals/fmsd/Bolognesi96,
  author       = {Tommaso Bolognesi},
  title        = {Regrouping Parallel Processes},
  journal      = {Formal Methods Syst. Des.},
  volume       = {9},
  number       = {3},
  pages        = {263--302},
  year         = {1996},
  url          = {https://doi.org/10.1007/BF00122084},
  doi          = {10.1007/BF00122084},
  timestamp    = {Fri, 13 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/fmsd/Bolognesi96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/fmsd/ClarkeJEF96,
  author       = {Edmund M. Clarke and
                  Somesh Jha and
                  Reinhard Enders and
                  Thomas Filkorn},
  title        = {Exploiting Symmetry in Temporal Logic Model Checking},
  journal      = {Formal Methods Syst. Des.},
  volume       = {9},
  number       = {1/2},
  pages        = {77--104},
  year         = {1996},
  url          = {https://doi.org/10.1007/BF00625969},
  doi          = {10.1007/BF00625969},
  timestamp    = {Fri, 13 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/fmsd/ClarkeJEF96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/fmsd/EmersonS96,
  author       = {E. Allen Emerson and
                  A. Prasad Sistla},
  title        = {Symmetry and Model Checking},
  journal      = {Formal Methods Syst. Des.},
  volume       = {9},
  number       = {1/2},
  pages        = {105--131},
  year         = {1996},
  url          = {https://doi.org/10.1007/BF00625970},
  doi          = {10.1007/BF00625970},
  timestamp    = {Fri, 13 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/fmsd/EmersonS96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/fmsd/IpD96,
  author       = {C. Norris Ip and
                  David L. Dill},
  title        = {Better Verification Through Symmetry},
  journal      = {Formal Methods Syst. Des.},
  volume       = {9},
  number       = {1/2},
  pages        = {41--75},
  year         = {1996},
  url          = {https://doi.org/10.1007/BF00625968},
  doi          = {10.1007/BF00625968},
  timestamp    = {Fri, 13 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/fmsd/IpD96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/fmsd/Jensen96,
  author       = {Kurt Jensen},
  title        = {Condensed State Spaces for Symmetrical Coloured Petri Nets},
  journal      = {Formal Methods Syst. Des.},
  volume       = {9},
  number       = {1/2},
  pages        = {7--40},
  year         = {1996},
  url          = {https://doi.org/10.1007/BF00625967},
  doi          = {10.1007/BF00625967},
  timestamp    = {Fri, 13 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/fmsd/Jensen96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/fmsd/Marcus96,
  author       = {Leo Marcus},
  title        = {The Incorporation of Testing into Formal Verification: Direct, Modular,
                  and Hierarchical Correctness Degrees},
  journal      = {Formal Methods Syst. Des.},
  volume       = {9},
  number       = {3},
  pages        = {235--261},
  year         = {1996},
  url          = {https://doi.org/10.1007/BF00122083},
  doi          = {10.1007/BF00122083},
  timestamp    = {Fri, 13 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/fmsd/Marcus96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/fmsd/YakovlevKKLP96,
  author       = {Alexandre Yakovlev and
                  Michael Kishinevsky and
                  Alex Kondratyev and
                  Luciano Lavagno and
                  Marta Pietkiewicz{-}Koutny},
  title        = {On the Models for Asynchronous Circuit Behaviour with {OR} Causality},
  journal      = {Formal Methods Syst. Des.},
  volume       = {9},
  number       = {3},
  pages        = {189--233},
  year         = {1996},
  url          = {https://doi.org/10.1007/BF00122082},
  doi          = {10.1007/BF00122082},
  timestamp    = {Fri, 13 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/fmsd/YakovlevKKLP96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/fmsd/YakovlevLS96,
  author       = {Alexandre Yakovlev and
                  Luciano Lavagno and
                  Alberto L. Sangiovanni{-}Vincentelli},
  title        = {A Unified Signal Transition Graph Model for Asynchronous Control Circuit
                  Synthesis},
  journal      = {Formal Methods Syst. Des.},
  volume       = {9},
  number       = {3},
  pages        = {139--188},
  year         = {1996},
  url          = {https://doi.org/10.1007/BF00122081},
  doi          = {10.1007/BF00122081},
  timestamp    = {Fri, 13 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/fmsd/YakovlevLS96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}