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export results for "toc:db/conf/slip/slip2014.bht:"
@inproceedings{DBLP:conf/slip/ChanKN14, author = {Wei{-}Ting Jonas Chan and Andrew B. Kahng and Siddhartha Nath}, title = {Methodology for electromigration signoff in the presence of adaptive voltage scaling}, booktitle = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction, {SLIP} 2014, San Francisco, CA, USA, June 1, 2014}, pages = {6:1--6:7}, publisher = {{IEEE} Computer Society}, year = {2014}, url = {https://doi.org/10.1145/2633948.2633950}, doi = {10.1145/2633948.2633950}, timestamp = {Wed, 16 Oct 2019 14:14:55 +0200}, biburl = {https://dblp.org/rec/conf/slip/ChanKN14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/slip/HuangWW14, author = {Tsung{-}Wei Huang and Pei{-}Ci Wu and Martin D. F. Wong}, title = {UI-route: An ultra-fast incremental maze routing algorithm}, booktitle = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction, {SLIP} 2014, San Francisco, CA, USA, June 1, 2014}, pages = {4:1--4:8}, publisher = {{IEEE} Computer Society}, year = {2014}, url = {https://doi.org/10.1145/2633948.2633952}, doi = {10.1145/2633948.2633952}, timestamp = {Sun, 02 Oct 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/slip/HuangWW14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/slip/KemmererT14, author = {Julian Kemmerer and Baris Taskin}, title = {Range-based dynamic routing of hierarchical on chip network traffic}, booktitle = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction, {SLIP} 2014, San Francisco, CA, USA, June 1, 2014}, pages = {5:1--5:9}, publisher = {{IEEE} Computer Society}, year = {2014}, url = {https://ieeexplore.ieee.org/document/6886040/}, timestamp = {Wed, 11 Aug 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/slip/KemmererT14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/slip/VaisbandF14, author = {Inna Vaisband and Eby G. Friedman}, title = {Power network-on-chip for scalable power delivery}, booktitle = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction, {SLIP} 2014, San Francisco, CA, USA, June 1, 2014}, pages = {1:1--1:5}, publisher = {{IEEE} Computer Society}, year = {2014}, url = {https://doi.org/10.1145/2633948.2633949}, doi = {10.1145/2633948.2633949}, timestamp = {Wed, 24 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/slip/VaisbandF14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/slip/ZhangLLC14, author = {Xiang Zhang and Jingwei Lu and Yang Liu and Chung{-}Kuan Cheng}, title = {Worst-case noise area prediciton of on-chip power distribution network}, booktitle = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction, {SLIP} 2014, San Francisco, CA, USA, June 1, 2014}, pages = {2:1--2:8}, publisher = {{IEEE} Computer Society}, year = {2014}, url = {https://doi.org/10.1145/2633948.2633951}, doi = {10.1145/2633948.2633951}, timestamp = {Wed, 24 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/slip/ZhangLLC14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/slip/ZhouRPKQLAS14, author = {Nancy Y. Zhou and Phillip J. Restle and Joseph N. Palumbo and Joseph N. Kozhaya and Haifeng Qian and Zhuo Li and Charles J. Alpert and Cliff C. N. Sze}, title = {Pacman: driving nonuniform clock grid loads for low-skew robust clock network}, booktitle = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction, {SLIP} 2014, San Francisco, CA, USA, June 1, 2014}, pages = {3:1--3:5}, publisher = {{IEEE} Computer Society}, year = {2014}, url = {https://doi.org/10.1145/2633948.2633953}, doi = {10.1145/2633948.2633953}, timestamp = {Fri, 25 Feb 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/slip/ZhouRPKQLAS14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/slip/Zou014, author = {Qiaosha Zou and Yuan Xie}, title = {Compact models and model standard for 2.5D and 3D integration}, booktitle = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction, {SLIP} 2014, San Francisco, CA, USA, June 1, 2014}, pages = {7:1--7:7}, publisher = {{IEEE} Computer Society}, year = {2014}, url = {https://doi.org/10.1145/2633948.2633955}, doi = {10.1145/2633948.2633955}, timestamp = {Wed, 24 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/slip/Zou014.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@proceedings{DBLP:conf/slip/2014, title = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction, {SLIP} 2014, San Francisco, CA, USA, June 1, 2014}, publisher = {{IEEE} Computer Society}, year = {2014}, url = {https://ieeexplore.ieee.org/xpl/conhome/6872646/proceeding}, isbn = {978-1-4503-3053-4}, timestamp = {Wed, 16 Oct 2019 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/slip/2014.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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