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@inproceedings{DBLP:conf/slip/BezerraFFDZ10,
  author       = {George B. P. Bezerra and
                  Stephanie Forrest and
                  Melanie Forrest and
                  Al Davis and
                  Payman Zarkesh{-}Ha},
  editor       = {Sherief Reda and
                  Janet Meiling Wang},
  title        = {Modeling NoC traffic locality and energy consumption with rent's communication
                  probability distribution},
  booktitle    = {International Workshop on System Level Interconnect Prediction Workshop,
                  {SLIP} 2010, Anaheim, CA, USA, June 13, 2010},
  pages        = {3--8},
  publisher    = {{ACM}},
  year         = {2010},
  url          = {https://doi.org/10.1145/1811100.1811103},
  doi          = {10.1145/1811100.1811103},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/BezerraFFDZ10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/Borkar10,
  author       = {Shekhar Y. Borkar},
  editor       = {Sherief Reda and
                  Janet Meiling Wang},
  title        = {Future of interconnect fabric: a contrarian view},
  booktitle    = {International Workshop on System Level Interconnect Prediction Workshop,
                  {SLIP} 2010, Anaheim, CA, USA, June 13, 2010},
  pages        = {1--2},
  publisher    = {{ACM}},
  year         = {2010},
  url          = {https://doi.org/10.1145/1811100.1811101},
  doi          = {10.1145/1811100.1811101},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/Borkar10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/ChengAKS10,
  author       = {Chung{-}Kuan Cheng and
                  Andrew B. Kahng and
                  Kambiz Samadi and
                  Amirali Shayan Arani},
  editor       = {Sherief Reda and
                  Janet Meiling Wang},
  title        = {Worst-case performance prediction under supply voltage and temperature
                  variation},
  booktitle    = {International Workshop on System Level Interconnect Prediction Workshop,
                  {SLIP} 2010, Anaheim, CA, USA, June 13, 2010},
  pages        = {91--96},
  publisher    = {{ACM}},
  year         = {2010},
  url          = {https://doi.org/10.1145/1811100.1811121},
  doi          = {10.1145/1811100.1811121},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/ChengAKS10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/CondleyHG10,
  author       = {Walter James Condley and
                  Xuchu Hu and
                  Matthew R. Guthaus},
  editor       = {Sherief Reda and
                  Janet Meiling Wang},
  title        = {Analysis of high-performance clock networks with {RLC} and transmission
                  line effects},
  booktitle    = {International Workshop on System Level Interconnect Prediction Workshop,
                  {SLIP} 2010, Anaheim, CA, USA, June 13, 2010},
  pages        = {51--58},
  publisher    = {{ACM}},
  year         = {2010},
  url          = {https://doi.org/10.1145/1811100.1811113},
  doi          = {10.1145/1811100.1811113},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/CondleyHG10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/GroeneveldSS10,
  author       = {Patrick Groeneveld and
                  Louis Scheffer and
                  Dirk Stroobandt},
  editor       = {Sherief Reda and
                  Janet Meiling Wang},
  title        = {{SLIP:} 10 years ago and 10 years from now},
  booktitle    = {International Workshop on System Level Interconnect Prediction Workshop,
                  {SLIP} 2010, Anaheim, CA, USA, June 13, 2010},
  pages        = {67--68},
  publisher    = {{ACM}},
  year         = {2010},
  url          = {https://doi.org/10.1145/1811100.1811116},
  doi          = {10.1145/1811100.1811116},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/GroeneveldSS10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/KimL10,
  author       = {Daehyun Kim and
                  Sung Kyu Lim},
  editor       = {Sherief Reda and
                  Janet Meiling Wang},
  title        = {Through-silicon-via-aware delay and power prediction model for buffered
                  interconnects in 3D ICs},
  booktitle    = {International Workshop on System Level Interconnect Prediction Workshop,
                  {SLIP} 2010, Anaheim, CA, USA, June 13, 2010},
  pages        = {25--32},
  publisher    = {{ACM}},
  year         = {2010},
  url          = {https://doi.org/10.1145/1811100.1811108},
  doi          = {10.1145/1811100.1811108},
  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/slip/KimL10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/LiML10,
  author       = {Di{-}An Li and
                  Malgorzata Marek{-}Sadowska and
                  Bill Lee},
  editor       = {Sherief Reda and
                  Janet Meiling Wang},
  title        = {On-chip em-sensitive interconnect structures},
  booktitle    = {International Workshop on System Level Interconnect Prediction Workshop,
                  {SLIP} 2010, Anaheim, CA, USA, June 13, 2010},
  pages        = {43--50},
  publisher    = {{ACM}},
  year         = {2010},
  url          = {https://doi.org/10.1145/1811100.1811112},
  doi          = {10.1145/1811100.1811112},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/LiML10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/MoreT10,
  author       = {Ankit More and
                  Baris Taskin},
  editor       = {Sherief Reda and
                  Janet Meiling Wang},
  title        = {Simulation based study of wireless {RF} interconnects for practical
                  CMOs implementation},
  booktitle    = {International Workshop on System Level Interconnect Prediction Workshop,
                  {SLIP} 2010, Anaheim, CA, USA, June 13, 2010},
  pages        = {35--42},
  publisher    = {{ACM}},
  year         = {2010},
  url          = {https://doi.org/10.1145/1811100.1811111},
  doi          = {10.1145/1811100.1811111},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/MoreT10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/QiuRH10,
  author       = {Jinhai Qiu and
                  Sherief Reda and
                  Soha Hassoun},
  editor       = {Sherief Reda and
                  Janet Meiling Wang},
  title        = {Fast, accurate a priori routing delay estimation},
  booktitle    = {International Workshop on System Level Interconnect Prediction Workshop,
                  {SLIP} 2010, Anaheim, CA, USA, June 13, 2010},
  pages        = {77--82},
  publisher    = {{ACM}},
  year         = {2010},
  url          = {https://doi.org/10.1145/1811100.1811119},
  doi          = {10.1145/1811100.1811119},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/QiuRH10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/Suaris10,
  author       = {Peter Ramyalal Suaris},
  editor       = {Sherief Reda and
                  Janet Meiling Wang},
  title        = {Application of 3-D ICs to FPGAs},
  booktitle    = {International Workshop on System Level Interconnect Prediction Workshop,
                  {SLIP} 2010, Anaheim, CA, USA, June 13, 2010},
  pages        = {15--16},
  publisher    = {{ACM}},
  year         = {2010},
  url          = {https://doi.org/10.1145/1811100.1811106},
  doi          = {10.1145/1811100.1811106},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/Suaris10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/Topaloglu10,
  author       = {Rasit Onur Topaloglu},
  editor       = {Sherief Reda and
                  Janet Meiling Wang},
  title        = {3-2-1 contact: an experimental approach to the analysisof contacts
                  in 45 nm and below},
  booktitle    = {International Workshop on System Level Interconnect Prediction Workshop,
                  {SLIP} 2010, Anaheim, CA, USA, June 13, 2010},
  pages        = {59--66},
  publisher    = {{ACM}},
  year         = {2010},
  url          = {https://doi.org/10.1145/1811100.1811114},
  doi          = {10.1145/1811100.1811114},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/Topaloglu10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/Wong10,
  author       = {Martin D. F. Wong},
  editor       = {Sherief Reda and
                  Janet Meiling Wang},
  title        = {Advances in {PCB} routing},
  booktitle    = {International Workshop on System Level Interconnect Prediction Workshop,
                  {SLIP} 2010, Anaheim, CA, USA, June 13, 2010},
  pages        = {33--34},
  publisher    = {{ACM}},
  year         = {2010},
  url          = {https://doi.org/10.1145/1811100.1811110},
  doi          = {10.1145/1811100.1811110},
  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/slip/Wong10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/XuPM10,
  author       = {Hu Xu and
                  Vasilis F. Pavlidis and
                  Giovanni De Micheli},
  editor       = {Sherief Reda and
                  Janet Meiling Wang},
  title        = {Process-induced skew variation for scaled 2-D and 3-D ICs},
  booktitle    = {International Workshop on System Level Interconnect Prediction Workshop,
                  {SLIP} 2010, Anaheim, CA, USA, June 13, 2010},
  pages        = {17--24},
  publisher    = {{ACM}},
  year         = {2010},
  url          = {https://doi.org/10.1145/1811100.1811107},
  doi          = {10.1145/1811100.1811107},
  timestamp    = {Thu, 11 Aug 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/slip/XuPM10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/YamanagaMS10,
  author       = {Koh Yamanaga and
                  Kazuya Masu and
                  Takashi Sato},
  editor       = {Sherief Reda and
                  Janet Meiling Wang},
  title        = {Application of generalized scattering matrix for prediction of power
                  supply noise},
  booktitle    = {International Workshop on System Level Interconnect Prediction Workshop,
                  {SLIP} 2010, Anaheim, CA, USA, June 13, 2010},
  pages        = {83--90},
  publisher    = {{ACM}},
  year         = {2010},
  url          = {https://doi.org/10.1145/1811100.1811120},
  doi          = {10.1145/1811100.1811120},
  timestamp    = {Tue, 07 May 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/slip/YamanagaMS10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/Zarkesh-HaBFM10,
  author       = {Payman Zarkesh{-}Ha and
                  George B. P. Bezerra and
                  Stephanie Forrest and
                  Melanie E. Moses},
  editor       = {Sherief Reda and
                  Janet Meiling Wang},
  title        = {Hybrid network on chip (HNoC): local buses with a global mesh architecture},
  booktitle    = {International Workshop on System Level Interconnect Prediction Workshop,
                  {SLIP} 2010, Anaheim, CA, USA, June 13, 2010},
  pages        = {9--14},
  publisher    = {{ACM}},
  year         = {2010},
  url          = {https://doi.org/10.1145/1811100.1811104},
  doi          = {10.1145/1811100.1811104},
  timestamp    = {Tue, 21 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/Zarkesh-HaBFM10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/ZhangBC10,
  author       = {Yulei Zhang and
                  James F. Buckwalter and
                  Chung{-}Kuan Cheng},
  editor       = {Sherief Reda and
                  Janet Meiling Wang},
  title        = {Performance prediction of throughput-centric pipelined global interconnects
                  with voltage scaling},
  booktitle    = {International Workshop on System Level Interconnect Prediction Workshop,
                  {SLIP} 2010, Anaheim, CA, USA, June 13, 2010},
  pages        = {69--76},
  publisher    = {{ACM}},
  year         = {2010},
  url          = {https://doi.org/10.1145/1811100.1811118},
  doi          = {10.1145/1811100.1811118},
  timestamp    = {Thu, 10 Oct 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/slip/ZhangBC10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@proceedings{DBLP:conf/slip/2010,
  editor       = {Sherief Reda and
                  Janet Meiling Wang},
  title        = {International Workshop on System Level Interconnect Prediction Workshop,
                  {SLIP} 2010, Anaheim, CA, USA, June 13, 2010},
  publisher    = {{ACM}},
  year         = {2010},
  url          = {http://dl.acm.org/citation.cfm?id=1811100},
  isbn         = {978-1-4503-0037-7},
  timestamp    = {Wed, 25 Jan 2012 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/2010.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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