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@inproceedings{DBLP:conf/dasip/AoudiaGB16,
author = {Fay{\c{c}}al Ait Aoudia and
Matthieu Gautier and
Olivier Berder},
title = {Demo abstract: How fuzzy logic can enhance energy management in Wireless
Sensor nodes equipped by energy harvesters and wake-up radios},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {229--230},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853827},
doi = {10.1109/DASIP.2016.7853827},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/dasip/AoudiaGB16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/ArslanGKK16,
author = {Mehmet Ali Arslan and
Flavius Gruian and
Krzysztof Kuchcinski and
Andreas Karlsson},
title = {Code generation for a {SIMD} architecture with custom memory organisation},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {90--97},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853802},
doi = {10.1109/DASIP.2016.7853802},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dasip/ArslanGKK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/BasterretxeaMFC16,
author = {Koldo Basterretxea and
Unai Martinez{-}Corral and
Raul Finker and
In{\'{e}}s del Campo},
title = {ELM-based hyperspectral imagery processor for onboard real-time classification},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {43--50},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853795},
doi = {10.1109/DASIP.2016.7853795},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dasip/BasterretxeaMFC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/BeaucampsK16,
author = {Pierre{-}Edouard Beaucamps and
Fr{\'{e}}d{\'{e}}ric Blanc Kalray},
title = {Demo: MPPA\({}^{\mbox{{\textregistered}}}\) manycore processor towards
future {ADAS} system solutions},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {243--244},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853834},
doi = {10.1109/DASIP.2016.7853834},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dasip/BeaucampsK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/BendaoudiCL16,
author = {Hamza Bendaoudi and
Farida Cheriet and
J. M. Pierre Langlois},
title = {Memory efficient Multi-Scale Line Detector architecture for retinal
blood vessel segmentation},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {59--64},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853797},
doi = {10.1109/DASIP.2016.7853797},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dasip/BendaoudiCL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/Biglari-Abhari16,
author = {Morteza Biglari{-}Abhari},
title = {Session 4: Advanced hardware architectures},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {106},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853804},
doi = {10.1109/DASIP.2016.7853804},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dasip/Biglari-Abhari16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/BollengierNLL16,
author = {Th{\'{e}}otime Bollengier and
Mohamad Najem and
Jean{-}Christophe Le Lann and
Lo{\"{\i}}c Lagadec},
title = {Demo: Overlay architectures for heterogeneous {FPGA} cluster management},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {239--240},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853832},
doi = {10.1109/DASIP.2016.7853832},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dasip/BollengierNLL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/CuperlierMM16,
author = {Nicolas Cuperlier and
Fr{\'{e}}d{\'{e}}ric Demelo and
Beno{\^{\i}}t Miramond},
title = {FPGA-based bio-inspired architecture for multi-scale attentional vision},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {231--232},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853828},
doi = {10.1109/DASIP.2016.7853828},
timestamp = {Thu, 15 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dasip/CuperlierMM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/DaniloWCGCC16,
author = {Robin Danilo and
Hugues Nono Wouafo and
Cyrille Chavet and
Vincent Gripon and
Laura Conde{-}Canencia and
Philippe Coussy},
title = {Associative Memory based on clustered Neural Networks: Improved model
and architecture for Oriented Edge Detection},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {51--58},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853796},
doi = {10.1109/DASIP.2016.7853796},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dasip/DaniloWCGCC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/DelmasAD16,
author = {Patrice Delmas and
Rachel Ababou},
title = {Special session 2 Computer vision and Image analysis},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {199},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853819},
doi = {10.1109/DASIP.2016.7853819},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dasip/DelmasAD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/GeeDJBAN16,
author = {Trevor Gee and
Patrice Delmas and
Sylvain Joly and
Valentin Baron and
Rachel Ababou and
Jean{-}Fran{\c{c}}ois Nezan},
title = {A dedicated lightweight binocular stereo system for real-time depth-map
generation},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {215--221},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853822},
doi = {10.1109/DASIP.2016.7853822},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dasip/GeeDJBAN16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/GeorgakarakosHL16,
author = {Georgios Georgakarakos and
Simon Holmbacka and
Johan Lilius},
title = {Analysis on scalability and energy efficiency of {HEVC} decoding using
task-based programming model},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {34--41},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853793},
doi = {10.1109/DASIP.2016.7853793},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dasip/GeorgakarakosHL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/Goehringer16,
author = {Diana Goehringer},
title = {Session 3: Method and tools for system design},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {73},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853799},
doi = {10.1109/DASIP.2016.7853799},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dasip/Goehringer16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/HafidhiBD16,
author = {Mohamed Mourad Hafidhi and
Emmanuel Boutillon and
Arnaud Dion},
title = {Demo: Localisation in a faulty digital {GPS} receiver},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {223--224},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853824},
doi = {10.1109/DASIP.2016.7853824},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dasip/HafidhiBD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/HolandaCM16,
author = {Jos{\'{e}} Arnaldo Mascagni de Holanda and
Jo{\~{a}}o Manuel Paiva Cardoso and
Eduardo Marques},
title = {A pipelined multi-softcore approach for the {HOG} algorithm},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {146--153},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853811},
doi = {10.1109/DASIP.2016.7853811},
timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dasip/HolandaCM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/HouzetFK16,
author = {Dominique Houzet and
Virginie Fresse and
Hubert Konik},
title = {{FPGA} memory optimization for real-time imaging},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {176--182},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853816},
doi = {10.1109/DASIP.2016.7853816},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dasip/HouzetFK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/Juarez16,
author = {Eduardo Ju{\'{a}}rez},
title = {Session 1: {HEVC} in embedded systems},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {1},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853789},
doi = {10.1109/DASIP.2016.7853789},
timestamp = {Thu, 06 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dasip/Juarez16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/KomorkiewiczTSK16,
author = {Mateusz Komorkiewicz and
Krzysztof Turek and
Pawel Skruch and
Tomasz Kryjak and
Marek Gorgon},
title = {FPGA-based Hardware-in-the-Loop environment using video injection
concept for camera-based systems in automotive applications},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {183--190},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853817},
doi = {10.1109/DASIP.2016.7853817},
timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dasip/KomorkiewiczTSK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/KrutschN16,
author = {Robert Krutsch and
Sharath Naidu},
title = {Monte Carlo method based precision analysis of deep convolution nets},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {162--167},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853814},
doi = {10.1109/DASIP.2016.7853814},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dasip/KrutschN16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/Langlois16,
author = {Pierre Langlois},
title = {Session 5: Image processing on multicore plateforms},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {129},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853808},
doi = {10.1109/DASIP.2016.7853808},
timestamp = {Thu, 18 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dasip/Langlois16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/LangloisMM16,
author = {Pierre Langlois and
Kevin J. M. Martin and
Eduardo Ju{\'{a}}rez Mart{\'{\i}}nez},
title = {Demo Night},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {222},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853823},
doi = {10.1109/DASIP.2016.7853823},
timestamp = {Thu, 18 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dasip/LangloisMM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/LemaitreL16,
author = {Florian Lemaitre and
Lionel Lacassagne},
title = {Batched Cholesky factorization for tiny matrices},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {130--137},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853809},
doi = {10.1109/DASIP.2016.7853809},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dasip/LemaitreL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/LiFVXPRHTB16,
author = {Lin Li and
Tiziana Fanni and
Timo Viitanen and
Renjie Xie and
Francesca Palumbo and
Luigi Raffo and
Heikki Huttunen and
Jarmo Takala and
Shuvra S. Bhattacharyya},
title = {Low power design methodology for signal processing systems using lightweight
dataflow techniques},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {82--89},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853801},
doi = {10.1109/DASIP.2016.7853801},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dasip/LiFVXPRHTB16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/MadronalLFOCJS16,
author = {Daniel Madro{\~{n}}al and
Raquel Lazcano and
Himar Fabelo and
Samuel Ortega and
Gustavo Marrero Callic{\'{o}} and
Eduardo Ju{\'{a}}rez and
C{\'{e}}sar Sanz},
title = {Hyperspectral image classification using a parallel implementation
of the linear {SVM} on a Massively Parallel Processor Array {(MPPA)}
platform},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {154--160},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853812},
doi = {10.1109/DASIP.2016.7853812},
timestamp = {Thu, 06 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dasip/MadronalLFOCJS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/MeinlKB16,
author = {Frank Meinl and
Martin Kunert and
Holger Blume},
title = {Hardware acceleration of Maximum-Likelihood angle estimation for automotive
{MIMO} radars},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {168--175},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853815},
doi = {10.1109/DASIP.2016.7853815},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dasip/MeinlKB16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/MenantGNPM16,
author = {Judicael Menant and
Guillaume Gautier and
Jean{-}Fran{\c{c}}ois Nezan and
Muriel Pressigout and
Luce Morin},
title = {A comparison of cost construction methods onto a {C6678} platform
for stereo matching},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {208--214},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853821},
doi = {10.1109/DASIP.2016.7853821},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dasip/MenantGNPM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/MercatHPM16,
author = {Alexandre Mercat and
Wassim Hamidouche and
Maxime Pelcat and
Daniel M{\'{e}}nard},
title = {Estimating encoding complexity of a real-time embedded software {HEVC}
codec},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {26--33},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853792},
doi = {10.1109/DASIP.2016.7853792},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dasip/MercatHPM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/MoreacRLB16,
author = {Erwan Moreac and
Andr{\'{e}} Rossi and
Johann Laurent and
Pierre Bomel},
title = {Crosstalk-aware link power model for Networks-on-Chip},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {121--128},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853807},
doi = {10.1109/DASIP.2016.7853807},
timestamp = {Thu, 15 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dasip/MoreacRLB16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/MoussawiD16,
author = {Ali Hassan El Moussawi and
Steven Derrien},
title = {Demo: SLP-aware word length optimization},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {233--234},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853829},
doi = {10.1109/DASIP.2016.7853829},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dasip/MoussawiD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/Palumbo16,
author = {Francesca Palumbo},
title = {Session 2: Architectures for image processing},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {42},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853794},
doi = {10.1109/DASIP.2016.7853794},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dasip/Palumbo16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/ParoisHMRD16,
author = {Ronan Parois and
Wassim Hamidouche and
Elie Gabriel Mora and
Micka{\"{e}}l Raulet and
Olivier D{\'{e}}forges},
title = {Efficient parallel architecture of an intra-only scalable multi-layer
{HEVC} encoder},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {11--17},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853790},
doi = {10.1109/DASIP.2016.7853790},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dasip/ParoisHMRD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/ParoisHMRD16a,
author = {Ronan Parois and
Wassim Hamidouche and
Elie Gabriel Mora and
Micka{\"{e}}l Raulet and
Olivier D{\'{e}}forges},
title = {Demo: {UHD} live video streaming with a real-time scalable {HEVC}
encoder},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {235--236},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853830},
doi = {10.1109/DASIP.2016.7853830},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dasip/ParoisHMRD16a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/RaffinHNPM16,
author = {Erwan Raffin and
Wassim Hamidouche and
Erwan Nogues and
Maxime Pelcat and
Daniel M{\'{e}}nard},
title = {Scalable {HEVC} decoder for mobile devices: Trade-off between energy
consumption and quality},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {18--25},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853791},
doi = {10.1109/DASIP.2016.7853791},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dasip/RaffinHNPM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/RihaniPNMM16,
author = {Mohamad Alfadl Rihani and
Jean{-}Christophe Pr{\'{e}}votet and
Fabienne Nouvel and
Mohamad Mrou{\'{e}} and
Yasser Mohanna},
title = {{ARM-FPGA} based platform for automated adaptive wireless communication
systems using partial reconfiguration technique},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {113--120},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853806},
doi = {10.1109/DASIP.2016.7853806},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dasip/RihaniPNMM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/SalemKM16,
author = {Khadija Hadj Salem and
Yann Kieffer and
St{\'{e}}phane Mancini},
title = {Memory management in embedded vision systems: Optimization problems
and solution methods},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {200--207},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853820},
doi = {10.1109/DASIP.2016.7853820},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dasip/SalemKM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/SalvadorFLOMCJS16,
author = {Rub{\'{e}}n Salvador and
Himar Fabelo and
Raquel Lazcano and
Samuel Ortega and
Daniel Madro{\~{n}}al and
Gustavo Marrero Callic{\'{o}} and
Eduardo Ju{\'{a}}rez and
C{\'{e}}sar Sanz},
title = {Demo: HELICoiD tool demonstrator for real-time brain cancer detection},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {237--238},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853831},
doi = {10.1109/DASIP.2016.7853831},
timestamp = {Thu, 06 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dasip/SalvadorFLOMCJS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/SantosGHS16,
author = {Lucana Santos and
Ana Gomez and
Pedro Hernandez{-}Fernandez and
Roberto Sarmiento},
title = {SystemC modelling of lossless compression {IP} cores for space applications},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {65--72},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853798},
doi = {10.1109/DASIP.2016.7853798},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dasip/SantosGHS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/SauFMRPP16,
author = {Carlo Sau and
Tiziana Fanni and
Paolo Meloni and
Luigi Raffo and
Maxime Pelcat and
Francesca Palumbo},
title = {Demo: Reconfigurable Platform Composer Tool},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {245--246},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853835},
doi = {10.1109/DASIP.2016.7853835},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dasip/SauFMRPP16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/SmetsGV16,
author = {Sander Smets and
Toon Goedem{\'{e}} and
Marian Verhelst},
title = {Custom processor design for efficient, yet flexible Lucas-Kanade optical
flow},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {138--145},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853810},
doi = {10.1109/DASIP.2016.7853810},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dasip/SmetsGV16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/StecheleKLHD16,
author = {Walter Stechele and
Tomasz Kryjak and
Lionel Lacassagne and
Dominique Houzet and
Martin Danek},
title = {Special session 1 automotive parallel computing challenges - architectures,
applications and tricks},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {161},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853813},
doi = {10.1109/DASIP.2016.7853813},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dasip/StecheleKLHD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/TanBS16,
author = {Benjamin Tan and
Morteza Biglari{-}Abhari and
Zoran Salcic},
title = {A system-level security approach for heterogeneous MPSoCs},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {74--81},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853800},
doi = {10.1109/DASIP.2016.7853800},
timestamp = {Mon, 29 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dasip/TanBS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/TchendjouAS16,
author = {Ghislain Takam Tchendjou and
Rshdee Alhakim and
Emmanuel Simeu},
title = {Fuzzy logic modeling for objective image quality assessment},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {98--105},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853803},
doi = {10.1109/DASIP.2016.7853803},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dasip/TchendjouAS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/TonnellierLGJGW16,
author = {Thibaud Tonnellier and
Camille Leroux and
Bertrand Le Gal and
Christophe J{\'{e}}go and
Benjamin Gadat and
Nicolas Van Wambeke},
title = {Hardware architecture for lowering the error floor of {LTE} turbo
codes},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {107--112},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853805},
doi = {10.1109/DASIP.2016.7853805},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dasip/TonnellierLGJGW16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/TranCG16,
author = {Mai{-}Thanh Tran and
Emmanuel Casseau and
Matthieu Gautier},
title = {Demo abstract: FPGA-based implementation of a flexible {FFT} dedicated
to {LTE} standard},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {241--242},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853833},
doi = {10.1109/DASIP.2016.7853833},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dasip/TranCG16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/WangCM16,
author = {Wenhao Wang and
Fabrice Camut and
Beno{\^{\i}}t Miramond},
title = {Generation of schedule tables on multi-core systems for {AUTOSAR}
applications},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {191--198},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853818},
doi = {10.1109/DASIP.2016.7853818},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dasip/WangCM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/XiaRPN16,
author = {Tian Xia and
Mohamad Alfadl Rihani and
Jean{-}Christophe Pr{\'{e}}votet and
Fabienne Nouvel},
title = {Demo: Ker-ONE: Embedded virtualization approach with dynamic reconfigurable
accelerators management},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {225--226},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853825},
doi = {10.1109/DASIP.2016.7853825},
timestamp = {Fri, 17 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dasip/XiaRPN16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/YuzugulerSIAATM16,
author = {Ahmet Caner Yuzuguler and
William Andrew Simon and
Aya Ibrahim and
Federico Angiolini and
Marcel Arditi and
Jean{-}Philippe Thiran and
Giovanni De Micheli},
title = {Demo: Efficient delay and apodization for on-FPGA 3D ultrasound},
booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
pages = {227--228},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/DASIP.2016.7853826},
doi = {10.1109/DASIP.2016.7853826},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dasip/YuzugulerSIAATM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/dasip/2016,
title = {2016 Conference on Design and Architectures for Signal and Image Processing
(DASIP), Rennes, France, October 12-14, 2016},
publisher = {{IEEE}},
year = {2016},
url = {https://ieeexplore.ieee.org/xpl/conhome/7845248/proceeding},
isbn = {979-1-0922-7915-3},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dasip/2016.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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