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@inproceedings{DBLP:conf/async/0014CCFALB18,
  author       = {Yang Zhang and
                  Huimei Cheng and
                  Dake Chen and
                  Huayu Fu and
                  Shikhanshu Agarwal and
                  Mark Lin and
                  Peter A. Beerel},
  title        = {Challenges in Building an Open-Source Flow from {RTL} to Bundled-Data
                  Design},
  booktitle    = {24th {IEEE} International Symposium on Asynchronous Circuits and Systems,
                  {ASYNC} 2018, Vienna, Austria, May 13-16, 2018},
  pages        = {26--27},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/ASYNC.2018.00015},
  doi          = {10.1109/ASYNC.2018.00015},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/async/0014CCFALB18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/async/BenafaSY18,
  author       = {Oyinkuro Benafa and
                  Danil Sokolov and
                  Alex Yakovlev},
  title        = {Loadable Kessels Counter},
  booktitle    = {24th {IEEE} International Symposium on Asynchronous Circuits and Systems,
                  {ASYNC} 2018, Vienna, Austria, May 13-16, 2018},
  pages        = {102--109},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/ASYNC.2018.00035},
  doi          = {10.1109/ASYNC.2018.00035},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/async/BenafaSY18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/async/BouzafourRG0S18,
  author       = {Aymane Bouzafour and
                  Marc Renaudin and
                  Hubert Garavel and
                  Radu Mateescu and
                  Wendelin Serwe},
  title        = {Model-Checking Synthesizable SystemVerilog Descriptions of Asynchronous
                  Circuits},
  booktitle    = {24th {IEEE} International Symposium on Asynchronous Circuits and Systems,
                  {ASYNC} 2018, Vienna, Austria, May 13-16, 2018},
  pages        = {34--42},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/ASYNC.2018.00021},
  doi          = {10.1109/ASYNC.2018.00021},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/async/BouzafourRG0S18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/async/ChauHKRS18,
  author       = {Cuong K. Chau and
                  Warren A. Hunt Jr. and
                  Matt Kaufmann and
                  Marly Roncken and
                  Ivan E. Sutherland},
  title        = {Data-Loop-Free Self-Timed Circuit Verification},
  booktitle    = {24th {IEEE} International Symposium on Asynchronous Circuits and Systems,
                  {ASYNC} 2018, Vienna, Austria, May 13-16, 2018},
  pages        = {51--58},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/ASYNC.2018.00023},
  doi          = {10.1109/ASYNC.2018.00023},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/async/ChauHKRS18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/async/DasLBS18,
  author       = {Shomit Das and
                  Michael LeBeane and
                  Bradford M. Beckmann and
                  Greg Sadowski},
  title        = {Case Study of Process Variation-Based Domain Partitioning of GPGPUs},
  booktitle    = {24th {IEEE} International Symposium on Asynchronous Circuits and Systems,
                  {ASYNC} 2018, Vienna, Austria, May 13-16, 2018},
  pages        = {119--120},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/ASYNC.2018.00037},
  doi          = {10.1109/ASYNC.2018.00037},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/async/DasLBS18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/async/FokB18,
  author       = {Sam Fok and
                  Kwabena Boahen},
  title        = {A Serial H-Tree Router for Two-Dimensional Arrays},
  booktitle    = {24th {IEEE} International Symposium on Asynchronous Circuits and Systems,
                  {ASYNC} 2018, Vienna, Austria, May 13-16, 2018},
  pages        = {78--85},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/ASYNC.2018.00026},
  doi          = {10.1109/ASYNC.2018.00026},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/async/FokB18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/async/FuggerKLW18,
  author       = {Matthias F{\"{u}}gger and
                  Attila Kinali and
                  Christoph Lenzen and
                  Ben Wiederhake},
  title        = {Fast All-Digital Clock Frequency Adaptation Circuit for Voltage Droop
                  Tolerance},
  booktitle    = {24th {IEEE} International Symposium on Asynchronous Circuits and Systems,
                  {ASYNC} 2018, Vienna, Austria, May 13-16, 2018},
  pages        = {68--77},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/ASYNC.2018.00025},
  doi          = {10.1109/ASYNC.2018.00025},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/async/FuggerKLW18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/async/GermainEF18,
  author       = {Sophie Germain and
                  Sylvain Engels and
                  Laurent Fesquet},
  title        = {A Design Flow for Shaping Electromagnetic Emissions in Micropipeline
                  Circuits},
  booktitle    = {24th {IEEE} International Symposium on Asynchronous Circuits and Systems,
                  {ASYNC} 2018, Vienna, Austria, May 13-16, 2018},
  pages        = {28--29},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/ASYNC.2018.00016},
  doi          = {10.1109/ASYNC.2018.00016},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/async/GermainEF18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/async/GimenezCCF18,
  author       = {Gregoire Gimenez and
                  Abdelkarim Cherkaoui and
                  Guillaume Cogniard and
                  Laurent Fesquet},
  title        = {Static Timing Analysis of Asynchronous Bundled-Data Circuits},
  booktitle    = {24th {IEEE} International Symposium on Asynchronous Circuits and Systems,
                  {ASYNC} 2018, Vienna, Austria, May 13-16, 2018},
  pages        = {110--118},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/ASYNC.2018.00036},
  doi          = {10.1109/ASYNC.2018.00036},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/async/GimenezCCF18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/async/HoppeDRRRS18,
  author       = {Christoph Hoppe and
                  Jens D{\"{o}}ge and
                  Peter Reichel and
                  Patrick Russell and
                  Andreas Reichel and
                  Peter Schneider},
  title        = {A High Speed Asynchronous Multi Input Pipeline for Compaction and
                  Transfer of Parallel {SIMD} Data},
  booktitle    = {24th {IEEE} International Symposium on Asynchronous Circuits and Systems,
                  {ASYNC} 2018, Vienna, Austria, May 13-16, 2018},
  pages        = {86--92},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/ASYNC.2018.00027},
  doi          = {10.1109/ASYNC.2018.00027},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/async/HoppeDRRRS18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/async/HuemerS18,
  author       = {Florian Huemer and
                  Andreas Steininger},
  title        = {Partially Systematic Constant-Weight Codes for Delay-Insensitive Communication},
  booktitle    = {24th {IEEE} International Symposium on Asynchronous Circuits and Systems,
                  {ASYNC} 2018, Vienna, Austria, May 13-16, 2018},
  pages        = {17--25},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/ASYNC.2018.00014},
  doi          = {10.1109/ASYNC.2018.00014},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/async/HuemerS18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/async/ImaiAY18,
  author       = {Masashi Imai and
                  Shinichiro Akasaka and
                  Tomohiro Yoneda},
  title        = {Novel Delay Elements for Bundled-Data Transfer Circuits Based on Two-Phase
                  Handshaking Protocols},
  booktitle    = {24th {IEEE} International Symposium on Asynchronous Circuits and Systems,
                  {ASYNC} 2018, Vienna, Austria, May 13-16, 2018},
  pages        = {1--8},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/ASYNC.2018.00012},
  doi          = {10.1109/ASYNC.2018.00012},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/async/ImaiAY18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/async/LinesJLMTWD18,
  author       = {Andrew Lines and
                  Prasad Joshi and
                  Ruokun Liu and
                  Steve McCoy and
                  Jonathan Tse and
                  Yi{-}Hsin Weng and
                  Mike Davies},
  title        = {Loihi Asynchronous Neuromorphic Research Chip},
  booktitle    = {24th {IEEE} International Symposium on Asynchronous Circuits and Systems,
                  {ASYNC} 2018, Vienna, Austria, May 13-16, 2018},
  pages        = {32--33},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/ASYNC.2018.00018},
  doi          = {10.1109/ASYNC.2018.00018},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/async/LinesJLMTWD18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/async/MorenoC18,
  author       = {Alberto Moreno and
                  Jordi Cortadella},
  title        = {State Encoding of Asynchronous Controllers Using Pseudo-Boolean Optimization},
  booktitle    = {24th {IEEE} International Symposium on Asynchronous Circuits and Systems,
                  {ASYNC} 2018, Vienna, Austria, May 13-16, 2018},
  pages        = {9--16},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/ASYNC.2018.00013},
  doi          = {10.1109/ASYNC.2018.00013},
  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/async/MorenoC18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/async/QiaoI18,
  author       = {Ning Qiao and
                  Giacomo Indiveri},
  title        = {A Clock-Less Ultra-Low Power Bit-Serial {LVDS} Link for Address-Event
                  Multi-chip Systems},
  booktitle    = {24th {IEEE} International Symposium on Asynchronous Circuits and Systems,
                  {ASYNC} 2018, Vienna, Austria, May 13-16, 2018},
  pages        = {93--101},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/ASYNC.2018.00028},
  doi          = {10.1109/ASYNC.2018.00028},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/async/QiaoI18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/async/ReiherGJ18,
  author       = {Justin Reiher and
                  Mark R. Greenstreet and
                  Ian W. Jones},
  title        = {Explaining Metastability in Real Synchronizers},
  booktitle    = {24th {IEEE} International Symposium on Asynchronous Circuits and Systems,
                  {ASYNC} 2018, Vienna, Austria, May 13-16, 2018},
  pages        = {59--67},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/ASYNC.2018.00024},
  doi          = {10.1109/ASYNC.2018.00024},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/async/ReiherGJ18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/async/SokolovKYL18,
  author       = {Danil Sokolov and
                  Victor Khomenko and
                  Alex Yakovlev and
                  David Lloyd},
  title        = {Design and Verification of Speed-Independent Circuits with Arbitration
                  in Workcraft},
  booktitle    = {24th {IEEE} International Symposium on Asynchronous Circuits and Systems,
                  {ASYNC} 2018, Vienna, Austria, May 13-16, 2018},
  pages        = {30--31},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/ASYNC.2018.00017},
  doi          = {10.1109/ASYNC.2018.00017},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/async/SokolovKYL18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/async/TarawnehM18,
  author       = {Ghaith Tarawneh and
                  Andrey Mokhov},
  title        = {Formal Verification of Mixed Synchronous Asynchronous Systems Using
                  Industrial Tools},
  booktitle    = {24th {IEEE} International Symposium on Asynchronous Circuits and Systems,
                  {ASYNC} 2018, Vienna, Austria, May 13-16, 2018},
  pages        = {43--50},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/ASYNC.2018.00022},
  doi          = {10.1109/ASYNC.2018.00022},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/async/TarawnehM18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@proceedings{DBLP:conf/async/2018,
  title        = {24th {IEEE} International Symposium on Asynchronous Circuits and Systems,
                  {ASYNC} 2018, Vienna, Austria, May 13-16, 2018},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://ieeexplore.ieee.org/xpl/conhome/8588203/proceeding},
  isbn         = {978-1-5386-5883-3},
  timestamp    = {Wed, 16 Oct 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/async/2018.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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