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@article{DBLP:journals/ieiceta/HirataK23,
author = {Tomonori Hirata and
Yuichi Kaji},
title = {Information Leakage Through Passive Timing Attacks on {RSA} Decryption
System},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {106},
number = {3},
pages = {406--413},
year = {2023},
url = {https://doi.org/10.1587/transfun.2022tap0006},
doi = {10.1587/TRANSFUN.2022TAP0006},
timestamp = {Thu, 09 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieiceta/HirataK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/istr/ChenHSJX22,
author = {Aidong Chen and
Chen Hong and
Xinna Shang and
Hongyuan Jing and
Sen Xu},
title = {Timing leakage to break {SM2} signature algorithm},
journal = {J. Inf. Secur. Appl.},
volume = {67},
pages = {103210},
year = {2022},
url = {https://doi.org/10.1016/j.jisa.2022.103210},
doi = {10.1016/J.JISA.2022.103210},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/istr/ChenHSJX22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cscml/DruckerP22,
author = {Nir Drucker and
Tomer Pelleg},
editor = {Shlomi Dolev and
Jonathan Katz and
Amnon Meisels},
title = {Timing Leakage Analysis of Non-constant-time {NTT} Implementations
with Harvey Butterflies},
booktitle = {Cyber Security, Cryptology, and Machine Learning - 6th International
Symposium, {CSCML} 2022, Be'er Sheva, Israel, June 30 - July 1, 2022,
Proceedings},
series = {Lecture Notes in Computer Science},
volume = {13301},
pages = {99--117},
publisher = {Springer},
year = {2022},
url = {https://doi.org/10.1007/978-3-031-07689-3\_8},
doi = {10.1007/978-3-031-07689-3\_8},
timestamp = {Tue, 28 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cscml/DruckerP22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/memocode/MorrisSC22,
author = {Eric Rothstein Morris and
Jun Sun and
Sudipta Chattopadhyay},
title = {{ORIGAMI:} Folding Data Structures to Reduce Timing Side-Channel Leakage},
booktitle = {20th {ACM-IEEE} International Conference on Formal Methods and Models
for System Design, {MEMOCODE} 2022, Shanghai, China, October 13-14,
2022},
pages = {1--12},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/MEMOCODE57689.2022.9954595},
doi = {10.1109/MEMOCODE57689.2022.9954595},
timestamp = {Wed, 07 Dec 2022 23:11:51 +0100},
biburl = {https://dblp.org/rec/conf/memocode/MorrisSC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iacr/ChaturvediCCM22,
author = {Bhuvnesh Chaturvedi and
Anirban Chakraborty and
Ayantika Chatterjee and
Debdeep Mukhopadhyay},
title = {Error Leakage using Timing Channel in {FHE} Ciphertexts from {TFHE}
Library},
journal = {{IACR} Cryptol. ePrint Arch.},
pages = {685},
year = {2022},
url = {https://eprint.iacr.org/2022/685},
timestamp = {Tue, 25 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iacr/ChaturvediCCM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iacr/DruckerP22,
author = {Nir Drucker and
Tomer Pelleg},
title = {Timing leakage analysis of non-constant-time {NTT} implementations
with Harvey butterflies},
journal = {{IACR} Cryptol. ePrint Arch.},
pages = {94},
year = {2022},
url = {https://eprint.iacr.org/2022/094},
timestamp = {Fri, 18 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/iacr/DruckerP22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieiceta/NakaiSOF21,
author = {Tsunato Nakai and
Daisuke Suzuki and
Fumio Omatsu and
Takeshi Fujino},
title = {Adversarial Black-Box Attacks with Timing Side-Channel Leakage},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {104-A},
number = {1},
pages = {143--151},
year = {2021},
url = {https://doi.org/10.1587/transfun.2020CIP0022},
doi = {10.1587/TRANSFUN.2020CIP0022},
timestamp = {Mon, 18 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieiceta/NakaiSOF21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/Biswas21,
author = {Arnab Kumar Biswas},
title = {Cryptographic Software {IP} Protection without Compromising Performance
or Timing Side-channel Leakage},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {18},
number = {2},
pages = {20:1--20:20},
year = {2021},
url = {https://doi.org/10.1145/3443707},
doi = {10.1145/3443707},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/taco/Biswas21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/GoliD21,
author = {Mehran Goli and
Rolf Drechsler},
title = {ATLaS: Automatic Detection of Timing-based Information Leakage Flows
for SystemC {HLS} Designs},
booktitle = {{ASPDAC} '21: 26th Asia and South Pacific Design Automation Conference,
Tokyo, Japan, January 18-21, 2021},
pages = {67--72},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3394885.3431591},
doi = {10.1145/3394885.3431591},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/GoliD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cardis/EscouteloupLFL21,
author = {Mathieu Escouteloup and
Ronan Lashermes and
Jacques Fournier and
Jean{-}Louis Lanet},
editor = {Vincent Grosso and
Thomas P{\"{o}}ppelmann},
title = {Under the Dome: Preventing Hardware Timing Information Leakage},
booktitle = {Smart Card Research and Advanced Applications - 20th International
Conference, {CARDIS} 2021, L{\"{u}}beck, Germany, November 11-12,
2021, Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {13173},
pages = {233--253},
publisher = {Springer},
year = {2021},
url = {https://doi.org/10.1007/978-3-030-97348-3\_13},
doi = {10.1007/978-3-030-97348-3\_13},
timestamp = {Thu, 10 Mar 2022 15:30:57 +0100},
biburl = {https://dblp.org/rec/conf/cardis/EscouteloupLFL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iacr/HlauschekLS21,
author = {Clemens Hlauschek and
Norman Lahr and
Robin Leander Schr{\"{o}}der},
title = {On the Timing Leakage of the Deterministic Re-encryption in {HQC}
{KEM}},
journal = {{IACR} Cryptol. ePrint Arch.},
pages = {1485},
year = {2021},
url = {https://eprint.iacr.org/2021/1485},
timestamp = {Fri, 10 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/iacr/HlauschekLS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/JiangFK20,
author = {Zhen Hang Jiang and
Yunsi Fei and
David R. Kaeli},
title = {Exploiting Bank Conflict-based Side-channel Timing Leakage of GPUs},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {16},
number = {4},
pages = {42:1--42:24},
year = {2020},
url = {https://doi.org/10.1145/3361870},
doi = {10.1145/3361870},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/taco/JiangFK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isita/HirataK20,
author = {Tomonori Hirata and
Yuichi Kaji},
title = {Information leakage through passive timing attacks on {RSA} decryption
system},
booktitle = {International Symposium on Information Theory and Its Applications,
{ISITA} 2020, Kapolei, HI, USA, October 24-27, 2020},
pages = {392--396},
publisher = {{IEEE}},
year = {2020},
url = {https://ieeexplore.ieee.org/document/9366110},
timestamp = {Mon, 22 Mar 2021 15:48:59 +0100},
biburl = {https://dblp.org/rec/conf/isita/HirataK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/lmcs/CanonesKR19,
author = {Pablo Ca{\~{n}}ones and
Boris K{\"{o}}pf and
Jan Reineke},
title = {On the Incomparability of Cache Algorithms in Terms of Timing Leakage},
journal = {Log. Methods Comput. Sci.},
volume = {15},
number = {1},
year = {2019},
url = {https://doi.org/10.23638/LMCS-15(1:21)2019},
doi = {10.23638/LMCS-15(1:21)2019},
timestamp = {Wed, 04 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/lmcs/CanonesKR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tdsc/BaoS19,
author = {Chongxi Bao and
Ankur Srivastava},
title = {Reducing Timing Side-Channel Information Leakage Using 3D Integration},
journal = {{IEEE} Trans. Dependable Secur. Comput.},
volume = {16},
number = {4},
pages = {665--678},
year = {2019},
url = {https://doi.org/10.1109/TDSC.2017.2712156},
doi = {10.1109/TDSC.2017.2712156},
timestamp = {Thu, 18 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tdsc/BaoS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@phdthesis{DBLP:phd/tr/Atici18,
author = {Ali Can Atici},
title = {Methods for finding the sources of leakage in cache-timing attacks
and removing the profiling phase ({\"{O}}nbellek-zamanlama sald{\i}r{\i}lar{\i}nda
s{\i}z{\i}nt{\i} kaynaklar{\i}n{\i} bulmak ve ayr{\i}mlama faz{\i}n{\i}
kald{\i}rmak i{\c{c}}in metotlar)},
school = {Sabanc{\i} University, Turkey},
year = {2018},
url = {https://tez.yok.gov.tr/UlusalTezMerkezi/tezDetay.jsp?id=HGgzMOw9DpQKPHziV4EqHQ\&no=T\_gS4a1r9WgVQelRuoMxEg},
timestamp = {Sat, 04 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/phd/tr/Atici18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jolpe/SLPSKPPK18,
author = {Patanjali SLPSK and
Milan Patnaik and
Seetal Potluri and
V. Kamakoti},
title = {MLTimer: Leakage Power Minimization in Digital Circuits Using Machine
Learning and Adaptive Lazy Timing Analysis},
journal = {J. Low Power Electron.},
volume = {14},
number = {2},
pages = {285--301},
year = {2018},
url = {https://doi.org/10.1166/jolpe.2018.1549},
doi = {10.1166/JOLPE.2018.1549},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jolpe/SLPSKPPK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/AwekeA18a,
author = {Zelalem Birhanu Aweke and
Todd M. Austin},
editor = {Jan Madsen and
Ayse K. Coskun},
title = {{\O}zone: Efficient execution with zero timing leakage for modern
microarchitectures},
booktitle = {2018 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2018, Dresden, Germany, March 19-23, 2018},
pages = {1123--1128},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.23919/DATE.2018.8342179},
doi = {10.23919/DATE.2018.8342179},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/AwekeA18a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esorics/BalaganiCGGGLMM18,
author = {Kiran S. Balagani and
Mauro Conti and
Paolo Gasti and
Martin Georgiev and
Tristan Gurtler and
Daniele Lain and
Charissa Miller and
Kendall Molas and
Nikita Samarin and
Eugen Saraci and
Gene Tsudik and
Lynn Wu},
editor = {Javier L{\'{o}}pez and
Jianying Zhou and
Miguel Soriano},
title = {{SILK-TV:} Secret Information Leakage from Keystroke Timing Videos},
booktitle = {Computer Security - 23rd European Symposium on Research in Computer
Security, {ESORICS} 2018, Barcelona, Spain, September 3-7, 2018, Proceedings,
Part {I}},
series = {Lecture Notes in Computer Science},
volume = {11098},
pages = {263--280},
publisher = {Springer},
year = {2018},
url = {https://doi.org/10.1007/978-3-319-99073-6\_13},
doi = {10.1007/978-3-319-99073-6\_13},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/esorics/BalaganiCGGGLMM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/LiuCWWL18,
author = {Chien{-}Tung Liu and
Zhe{-}Wei Chang and
Shih{-}Nung Wei and
Jinn{-}Shyan Wang and
Tay{-}Jyi Lin},
title = {A Low-Area, Low-Power, and Low-Leakage Error-Detecting Latch for Timing-Error
Resilient System Designs},
booktitle = {31st {IEEE} International System-on-Chip Conference, {SOCC} 2018,
Arlington, VA, USA, September 4-7, 2018},
pages = {1--6},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/SOCC.2018.8618543},
doi = {10.1109/SOCC.2018.8618543},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/socc/LiuCWWL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/wscad/NapoliRAB18,
author = {Ot{\'{a}}vio Oliveira Napoli and
Vanderson Martins do Ros{\'{a}}rio and
Diego de Freitas Aranha and
Edson Borin},
title = {Evaluation of Timing Side-Channel Leakage on a Multiple-Target Dynamic
Binary Translator},
booktitle = {Symposium on High Performance Computing Systems, {WSCAD} 2018, S{\~{a}}o
Paulo, Brazil, October 1-3, 2018},
pages = {198--204},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/WSCAD.2018.00039},
doi = {10.1109/WSCAD.2018.00039},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/wscad/NapoliRAB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/wscad/NapoliRAB18a,
author = {Ot{\'{a}}vio Oliveira Napoli and
Vanderson Martins do Rosario and
Diego de Freitas Aranha and
Edson Borin},
editor = {Calebe P. Bianchini and
Carla Osthoff and
Paulo Souza and
Renato Ferreira},
title = {Evaluation and Mitigation of Timing Side-Channel Leakages on Multiple-Target
Dynamic Binary Translators},
booktitle = {High Performance Computing Systems - 19th Symposium, {WSCAD} 2018,
S{\~{a}}o Paulo, Brazil, October 1-3, 2018, Revised Selected Papers},
series = {Communications in Computer and Information Science},
volume = {1171},
pages = {152--167},
publisher = {Springer},
year = {2018},
url = {https://doi.org/10.1007/978-3-030-41050-6\_10},
doi = {10.1007/978-3-030-41050-6\_10},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/wscad/NapoliRAB18a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1807-01240,
author = {Pablo Ca{\~{n}}ones and
Boris K{\"{o}}pf and
Jan Reineke},
title = {On the Incomparability of Cache Algorithms in Terms of Timing Leakage},
journal = {CoRR},
volume = {abs/1807.01240},
year = {2018},
url = {http://arxiv.org/abs/1807.01240},
eprinttype = {arXiv},
eprint = {1807.01240},
timestamp = {Wed, 04 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-1807-01240.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/host/AwekeA17,
author = {Zelalem Birhanu Aweke and
Todd M. Austin},
title = {{\O}zone: Efficient execution with zero timing leakage for modern
microarchitectures},
booktitle = {2017 {IEEE} International Symposium on Hardware Oriented Security
and Trust, {HOST} 2017, McLean, VA, USA, May 1-5, 2017},
pages = {153},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/HST.2017.7951817},
doi = {10.1109/HST.2017.7951817},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/host/AwekeA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/NishioKN17,
author = {Yuya Nishio and
Atsuki Kobayashi and
Kiichi Niitsu},
title = {A 28{\(\mu\)}m\({}^{\mbox{2}}\), 0.11Hz, 4.5pW gate leakage timer
using differential leakage technique in 55nm {DDC} {CMOS} for small-footprint,
low-frequency and low-power timing generation},
booktitle = {24th {IEEE} International Conference on Electronics, Circuits and
Systems, {ICECS} 2017, Batumi, Georgia, December 5-8, 2017},
pages = {368--371},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ICECS.2017.8292063},
doi = {10.1109/ICECS.2017.8292063},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icecsys/NishioKN17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/AwekeA17,
author = {Zelalem Birhanu Aweke and
Todd M. Austin},
title = {Ozone: Efficient Execution with Zero Timing Leakage for Modern Microarchitectures},
journal = {CoRR},
volume = {abs/1703.07706},
year = {2017},
url = {http://arxiv.org/abs/1703.07706},
eprinttype = {arXiv},
eprint = {1703.07706},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/AwekeA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ton/GongK16,
author = {Xun Gong and
Negar Kiyavash},
title = {Quantifying the Information Leakage in Timing Side Channels in Deterministic
Work-Conserving Schedulers},
journal = {{IEEE/ACM} Trans. Netw.},
volume = {24},
number = {3},
pages = {1841--1852},
year = {2016},
url = {https://doi.org/10.1109/TNET.2015.2438860},
doi = {10.1109/TNET.2015.2438860},
timestamp = {Fri, 23 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ton/GongK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/GonzalezMS15,
author = {George Gonzalez and
Murari Mani and
Mahesh Sharma},
title = {Large-scale multi-corner leakage optimization under the sign-off timing
environment},
booktitle = {Sixteenth International Symposium on Quality Electronic Design, {ISQED}
2015, Santa Clara, CA, USA, March 2-4, 2015},
pages = {40--45},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISQED.2015.7085395},
doi = {10.1109/ISQED.2015.7085395},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isqed/GonzalezMS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/HuangH14,
author = {Shi{-}Yu Huang and
Li{-}Ren Huang},
title = {PLL-Assisted Timing Circuit for Accurate {TSV} Leakage Binning},
journal = {{IEEE} Des. Test},
volume = {31},
number = {4},
pages = {36--42},
year = {2014},
url = {https://doi.org/10.1109/MDAT.2014.2335152},
doi = {10.1109/MDAT.2014.2335152},
timestamp = {Fri, 13 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/dt/HuangH14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/FletcherRYDKD14,
author = {Christopher W. Fletcher and
Ling Ren and
Xiangyao Yu and
Marten van Dijk and
Omer Khan and
Srinivas Devadas},
title = {Suppressing the Oblivious {RAM} timing channel while making information
leakage and program efficiency trade-offs},
booktitle = {20th {IEEE} International Symposium on High Performance Computer Architecture,
{HPCA} 2014, Orlando, FL, USA, February 15-19, 2014},
pages = {213--224},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/HPCA.2014.6835932},
doi = {10.1109/HPCA.2014.6835932},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hpca/FletcherRYDKD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/services/MarkenH14,
author = {Brandon Marken and
Brian Hay},
title = {Using Memory Map Timings to Discover Information Leakage to a Live
{VM} from the Hypervisor},
booktitle = {2014 {IEEE} World Congress on Services, {SERVICES} 2014, Anchorage,
AK, USA, June 27 - July 2, 2014},
pages = {48--52},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/SERVICES.2014.18},
doi = {10.1109/SERVICES.2014.18},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/services/MarkenH14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mj/ZhuBW13,
author = {Jiafeng Zhu and
Na Bai and
Jianhui Wu},
title = {A low active and leakage power {SRAM} using a read and write divided
and {BIST} programmable timing control circuit},
journal = {Microelectron. J.},
volume = {44},
number = {4},
pages = {283--291},
year = {2013},
url = {https://doi.org/10.1016/j.mejo.2013.02.009},
doi = {10.1016/J.MEJO.2013.02.009},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mj/ZhuBW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuangLHTC13,
author = {Shi{-}Yu Huang and
Yu{-}Hsiang Lin and
Li{-}Ren Huang and
Kun{-}Han Tsai and
Wu{-}Tung Cheng},
title = {Programmable Leakage Test and Binning for TSVs With Self-Timed Timing
Control},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {32},
number = {8},
pages = {1265--1273},
year = {2013},
url = {https://doi.org/10.1109/TCAD.2013.2252056},
doi = {10.1109/TCAD.2013.2252056},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuangLHTC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HwangKK13,
author = {Eun Ju Hwang and
Wook Kim and
Young Hwan Kim},
title = {Timing Yield Slack for Timing Yield-Constrained Optimization and Its
Application to Statistical Leakage Minimization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {21},
number = {10},
pages = {1783--1796},
year = {2013},
url = {https://doi.org/10.1109/TVLSI.2012.2220792},
doi = {10.1109/TVLSI.2012.2220792},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HwangKK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/RenD13,
author = {Huan Ren and
Shantanu Dutt},
title = {Fast and Near-Optimal Timing-Driven Cell Sizing under Cell Area and
Leakage Power Constraints Using a Simplified Discrete Network Flow
Algorithm},
journal = {{VLSI} Design},
volume = {2013},
pages = {474601:1--474601:15},
year = {2013},
url = {https://doi.org/10.1155/2013/474601},
doi = {10.1155/2013/474601},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/RenD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asicon/WangHLZY13,
author = {Nan Wang and
Cong Hao and
Nan Liu and
Haoran Zhang and
Takeshi Yoshimura},
title = {Timing and resource constrained leakage power aware scheduling in
high-level synthesis},
booktitle = {{IEEE} 10th International Conference on ASIC, {ASICON} 2013, Shenzhen,
China, October 28-31, 2013},
pages = {1--4},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ASICON.2013.6811939},
doi = {10.1109/ASICON.2013.6811939},
timestamp = {Tue, 14 Jan 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asicon/WangHLZY13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/infocom/KadloorKV12,
author = {Sachin Kadloor and
Negar Kiyavash and
Parv Venkitasubramaniam},
editor = {Albert G. Greenberg and
Kazem Sohraby},
title = {Mitigating timing based information leakage in shared schedulers},
booktitle = {Proceedings of the {IEEE} {INFOCOM} 2012, Orlando, FL, USA, March
25-30, 2012},
pages = {1044--1052},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/INFCOM.2012.6195460},
doi = {10.1109/INFCOM.2012.6195460},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/infocom/KadloorKV12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/ChenYCC11,
author = {Yi{-}Jung Chen and
Chia{-}Lin Yang and
Jaw{-}Wei Chi and
Jian{-}Jia Chen},
title = {{TACLC:} Timing-Aware Cache Leakage Control for Hard Real-Time Systems},
journal = {{IEEE} Trans. Computers},
volume = {60},
number = {6},
pages = {767--782},
year = {2011},
url = {https://doi.org/10.1109/TC.2011.44},
doi = {10.1109/TC.2011.44},
timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tc/ChenYCC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/KounalakisSZ11,
author = {Evriklis Kounalakis and
Christos P. Sotiriou and
Vassilis Zebilis},
title = {Statistical Timing-Based Post-Placement Leakage Recovery},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2011, 4-6
July 2011, Chennai, India},
pages = {102--107},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ISVLSI.2011.47},
doi = {10.1109/ISVLSI.2011.47},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/KounalakisSZ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JeongKPY10,
author = {Kwangok Jeong and
Andrew B. Kahng and
Chul{-}Hong Park and
Hailong Yao},
title = {Dose Map and Placement Co-Optimization for Improved Timing Yield and
Leakage Power},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {29},
number = {7},
pages = {1070--1082},
year = {2010},
url = {https://doi.org/10.1109/TCAD.2010.2048397},
doi = {10.1109/TCAD.2010.2048397},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JeongKPY10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/csfw/KopfS10,
author = {Boris K{\"{o}}pf and
Geoffrey Smith},
title = {Vulnerability Bounds and Leakage Resilience of Blinded Cryptography
under Timing Attacks},
booktitle = {Proceedings of the 23rd {IEEE} Computer Security Foundations Symposium,
{CSF} 2010, Edinburgh, United Kingdom, July 17-19, 2010},
pages = {44--56},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/CSF.2010.11},
doi = {10.1109/CSF.2010.11},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/csfw/KopfS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tim/KimKL09,
author = {Kyung Ki Kim and
Yong{-}Bin Kim and
Fabrizio Lombardi},
title = {A Novel Statistical Timing and Leakage Power Characterization of Partially
Depleted Silicon-on-Insulator Gates},
journal = {{IEEE} Trans. Instrum. Meas.},
volume = {58},
number = {2},
pages = {401--410},
year = {2009},
url = {https://doi.org/10.1109/TIM.2008.2003322},
doi = {10.1109/TIM.2008.2003322},
timestamp = {Mon, 08 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tim/KimKL09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/AndersonDLSK09,
author = {Michael J. Anderson and
Azadeh Davoodi and
Jungseob Lee and
Abhishek A. Sinkar and
Nam Sung Kim},
editor = {J{\"{o}}rg Henkel and
Ali Keshavarzi and
Naehyuck Chang and
Tahir Ghani},
title = {Statistical static timing analysis considering leakage variability
in power gated designs},
booktitle = {Proceedings of the 2009 International Symposium on Low Power Electronics
and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009},
pages = {57--62},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1594233.1594247},
doi = {10.1145/1594233.1594247},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/AndersonDLSK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/RedaSB09,
author = {Sherief Reda and
Aung Si and
R. Iris Bahar},
editor = {J{\"{o}}rg Henkel and
Ali Keshavarzi and
Naehyuck Chang and
Tahir Ghani},
title = {Reducing the leakage and timing variability of 2D ICcs using 3D ICs},
booktitle = {Proceedings of the 2009 International Symposium on Low Power Electronics
and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009},
pages = {283--286},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1594233.1594303},
doi = {10.1145/1594233.1594303},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/RedaSB09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BhardwajVG08,
author = {Sarvesh Bhardwaj and
Sarma B. K. Vrudhula and
Amit Goel},
title = {A Unified Approach for Full Chip Statistical Timing and Leakage Analysis
of Nanoscale Circuits Considering Intradie Process Variations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {10},
pages = {1812--1825},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.927671},
doi = {10.1109/TCAD.2008.927671},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BhardwajVG08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/JeongKPY08,
author = {Kwangok Jeong and
Andrew B. Kahng and
Chul{-}Hong Park and
Hailong Yao},
editor = {Limor Fix},
title = {Dose map and placement co-optimization for timing yield enhancement
and leakage power reduction},
booktitle = {Proceedings of the 45th Design Automation Conference, {DAC} 2008,
Anaheim, CA, USA, June 8-13, 2008},
pages = {516--521},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1391469.1391600},
doi = {10.1145/1391469.1391600},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/JeongKPY08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@phdthesis{DBLP:phd/basesearch/Choi07,
author = {Munkang Choi},
title = {Modeling of Deterministic Within-Die Variation in Timing Analysis,
Leakage current Analysis, and Delay Fault Diagnosis},
school = {Georgia Institute of Technology, Atlanta, GA, {USA}},
year = {2007},
url = {https://hdl.handle.net/1853/14544},
timestamp = {Wed, 04 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/phd/basesearch/Choi07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GuptaKKS07,
author = {Puneet Gupta and
Andrew B. Kahng and
Youngmin Kim and
Dennis Sylvester},
title = {Self-Compensating Design for Reduction of Timing and Leakage Sensitivity
to Systematic Pattern-Dependent Variation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {9},
pages = {1614--1624},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.895759},
doi = {10.1109/TCAD.2007.895759},
timestamp = {Thu, 28 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GuptaKKS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/HassanAE07,
author = {Hassan Hassan and
Mohab Anis and
Mohamed I. Elmasry},
title = {A Timing-Driven Algorithm for Leakage Reduction in {MTCMOS} FPGAs},
booktitle = {Proceedings of the 12th Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2007, Yokohama, Japan, January 23-26, 2007},
pages = {678--683},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ASPDAC.2007.358065},
doi = {10.1109/ASPDAC.2007.358065},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/HassanAE07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/LuA07,
author = {Yuanlin Lu and
Vishwani D. Agrawal},
title = {Statistical Leakage and Timing Optimization for Submicron Process
Variation},
booktitle = {20th International Conference on {VLSI} Design {(VLSI} Design 2007),
Sixth International Conference on Embedded Systems {(ICES} 2007),
6-10 January 2007, Bangalore, India},
pages = {439--444},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/VLSID.2007.148},
doi = {10.1109/VLSID.2007.148},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/LuA07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/csreaSAM/KarpinskyyVG06,
author = {Mykola Karpinskyy and
Lesya Vasylkiv and
Marcin Gizycki},
editor = {Hamid R. Arabnia and
Selim Aissi},
title = {Secret Key Leakage Caused by Hamming-weight Timing Analysis on Modular
Exponentiation},
booktitle = {Proceedings of the 2006 International Conference on Security {\&}
Management, {SAM} 2006, Las Vegas, Nevada, USA, June 26-29, 2006},
pages = {179--185},
publisher = {{CSREA} Press},
year = {2006},
timestamp = {Wed, 06 Dec 2006 10:51:51 +0100},
biburl = {https://dblp.org/rec/conf/csreaSAM/KarpinskyyVG06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/BhardwajCV06,
author = {Sarvesh Bhardwaj and
Yu Cao and
Sarma B. K. Vrudhula},
title = {{LOTUS:} Leakage Optimization under Timing Uncertainty for Standard-cell
designs},
booktitle = {7th International Symposium on Quality of Electronic Design {(ISQED}
2006), 27-29 March 2006, San Jose, CA, {USA}},
pages = {717--722},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/ISQED.2006.83},
doi = {10.1109/ISQED.2006.83},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/BhardwajCV06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/LiuG02,
author = {Yong Liu and
Zhiqiang Gao},
title = {Timing analysis of transistor stack for leakage power saving},
booktitle = {Proceedings of the 2002 9th {IEEE} International Conference on Electronics,
Circuits and Systems, {ICECS} 2002, Dubrovnik, Croatia, September
15-18, 2002},
pages = {41--44},
publisher = {{IEEE}},
year = {2002},
url = {https://doi.org/10.1109/ICECS.2002.1045328},
doi = {10.1109/ICECS.2002.1045328},
timestamp = {Mon, 09 Aug 2021 14:54:04 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/LiuG02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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