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@inproceedings{DBLP:conf/wmpi/BriggsCC04,
  author       = {Faye A. Briggs and
                  Suresh Chittor and
                  Kai Cheng},
  editor       = {John B. Carter and
                  Lixin Zhang},
  title        = {Micro-architecture techniques in the intel {E8870} scalable memory
                  controller},
  booktitle    = {Proceedings of the 3rd Workshop on Memory Performance Issues, in conjunction
                  with the 31st International Symposium on Computer Architecture 2004,
                  Munich, Germany, June 20, 2004},
  pages        = {30--36},
  publisher    = {{ACM}},
  year         = {2004},
  url          = {https://doi.org/10.1145/1054943.1054948},
  doi          = {10.1145/1054943.1054948},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/wmpi/BriggsCC04.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/wmpi/BrockmanTKK04,
  author       = {Jay B. Brockman and
                  Shyamkumar Thoziyoor and
                  Shannon K. Kuntz and
                  Peter M. Kogge},
  editor       = {John B. Carter and
                  Lixin Zhang},
  title        = {A low cost, multithreaded processing-in-memory system},
  booktitle    = {Proceedings of the 3rd Workshop on Memory Performance Issues, in conjunction
                  with the 31st International Symposium on Computer Architecture 2004,
                  Munich, Germany, June 20, 2004},
  pages        = {16--22},
  publisher    = {{ACM}},
  year         = {2004},
  url          = {https://doi.org/10.1145/1054943.1054946},
  doi          = {10.1145/1054943.1054946},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/wmpi/BrockmanTKK04.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/wmpi/ChihaiaG04,
  author       = {Irina Chihaia and
                  Thomas R. Gross},
  editor       = {John B. Carter and
                  Lixin Zhang},
  title        = {An analytical model for software-only main memory compression},
  booktitle    = {Proceedings of the 3rd Workshop on Memory Performance Issues, in conjunction
                  with the 31st International Symposium on Computer Architecture 2004,
                  Munich, Germany, June 20, 2004},
  pages        = {107--113},
  publisher    = {{ACM}},
  year         = {2004},
  url          = {https://doi.org/10.1145/1054943.1054958},
  doi          = {10.1145/1054943.1054958},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/wmpi/ChihaiaG04.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/wmpi/EkmanS04,
  author       = {Magnus Ekman and
                  Per Stenstr{\"{o}}m},
  editor       = {John B. Carter and
                  Lixin Zhang},
  title        = {A case for multi-level main memory},
  booktitle    = {Proceedings of the 3rd Workshop on Memory Performance Issues, in conjunction
                  with the 31st International Symposium on Computer Architecture 2004,
                  Munich, Germany, June 20, 2004},
  pages        = {1--8},
  publisher    = {{ACM}},
  year         = {2004},
  url          = {https://doi.org/10.1145/1054943.1054944},
  doi          = {10.1145/1054943.1054944},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/wmpi/EkmanS04.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/wmpi/GabrielW04,
  author       = {Steven T. Gabriel and
                  David S. Wise},
  editor       = {John B. Carter and
                  Lixin Zhang},
  title        = {The Opie compiler from row-major source to Morton-ordered matrices},
  booktitle    = {Proceedings of the 3rd Workshop on Memory Performance Issues, in conjunction
                  with the 31st International Symposium on Computer Architecture 2004,
                  Munich, Germany, June 20, 2004},
  pages        = {136--144},
  publisher    = {{ACM}},
  year         = {2004},
  url          = {https://doi.org/10.1145/1054943.1054962},
  doi          = {10.1145/1054943.1054962},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/wmpi/GabrielW04.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/wmpi/GalluzziBPGCV04,
  author       = {Marco Galluzzi and
                  Ram{\'{o}}n Beivide and
                  Valentin Puente and
                  Jos{\'{e}}{-}{\'{A}}ngel Gregorio and
                  Adri{\'{a}}n Cristal and
                  Mateo Valero},
  editor       = {John B. Carter and
                  Lixin Zhang},
  title        = {Evaluating kilo-instruction multiprocessors},
  booktitle    = {Proceedings of the 3rd Workshop on Memory Performance Issues, in conjunction
                  with the 31st International Symposium on Computer Architecture 2004,
                  Munich, Germany, June 20, 2004},
  pages        = {72--79},
  publisher    = {{ACM}},
  year         = {2004},
  url          = {https://doi.org/10.1145/1054943.1054953},
  doi          = {10.1145/1054943.1054953},
  timestamp    = {Sun, 12 Nov 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/wmpi/GalluzziBPGCV04.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/wmpi/GonzalezLG04,
  author       = {Jos{\'{e}} Gonz{\'{a}}lez and
                  Fernando Latorre and
                  Antonio Gonz{\'{a}}lez},
  editor       = {John B. Carter and
                  Lixin Zhang},
  title        = {Cache organizations for clustered microarchitectures},
  booktitle    = {Proceedings of the 3rd Workshop on Memory Performance Issues, in conjunction
                  with the 31st International Symposium on Computer Architecture 2004,
                  Munich, Germany, June 20, 2004},
  pages        = {46--55},
  publisher    = {{ACM}},
  year         = {2004},
  url          = {https://doi.org/10.1145/1054943.1054950},
  doi          = {10.1145/1054943.1054950},
  timestamp    = {Sat, 29 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/wmpi/GonzalezLG04.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/wmpi/HallnorR04,
  author       = {Erik G. Hallnor and
                  Steven K. Reinhardt},
  editor       = {John B. Carter and
                  Lixin Zhang},
  title        = {A compressed memory hierarchy using an indirect index cache},
  booktitle    = {Proceedings of the 3rd Workshop on Memory Performance Issues, in conjunction
                  with the 31st International Symposium on Computer Architecture 2004,
                  Munich, Germany, June 20, 2004},
  pages        = {9--15},
  publisher    = {{ACM}},
  year         = {2004},
  url          = {https://doi.org/10.1145/1054943.1054945},
  doi          = {10.1145/1054943.1054945},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/wmpi/HallnorR04.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/wmpi/McCurdyF04,
  author       = {Collin McCurdy and
                  Charles N. Fischer},
  editor       = {John B. Carter and
                  Lixin Zhang},
  title        = {A localizing directory coherence protocol},
  booktitle    = {Proceedings of the 3rd Workshop on Memory Performance Issues, in conjunction
                  with the 31st International Symposium on Computer Architecture 2004,
                  Munich, Germany, June 20, 2004},
  pages        = {23--29},
  publisher    = {{ACM}},
  year         = {2004},
  url          = {https://doi.org/10.1145/1054943.1054947},
  doi          = {10.1145/1054943.1054947},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/wmpi/McCurdyF04.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/wmpi/Mudawar04,
  author       = {Muhamed F. Mudawar},
  editor       = {John B. Carter and
                  Lixin Zhang},
  title        = {Scalable cache memory design for large-scale {SMT} architectures},
  booktitle    = {Proceedings of the 3rd Workshop on Memory Performance Issues, in conjunction
                  with the 31st International Symposium on Computer Architecture 2004,
                  Munich, Germany, June 20, 2004},
  pages        = {65--71},
  publisher    = {{ACM}},
  year         = {2004},
  url          = {https://doi.org/10.1145/1054943.1054952},
  doi          = {10.1145/1054943.1054952},
  timestamp    = {Thu, 14 Oct 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/wmpi/Mudawar04.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/wmpi/MutluKAP04,
  author       = {Onur Mutlu and
                  Hyesoon Kim and
                  David N. Armstrong and
                  Yale N. Patt},
  editor       = {John B. Carter and
                  Lixin Zhang},
  title        = {Understanding the effects of wrong-path memory references on processor
                  performance},
  booktitle    = {Proceedings of the 3rd Workshop on Memory Performance Issues, in conjunction
                  with the 31st International Symposium on Computer Architecture 2004,
                  Munich, Germany, June 20, 2004},
  pages        = {56--64},
  publisher    = {{ACM}},
  year         = {2004},
  url          = {https://doi.org/10.1145/1054943.1054951},
  doi          = {10.1145/1054943.1054951},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/wmpi/MutluKAP04.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/wmpi/NakarW04,
  author       = {Doron Nakar and
                  Shlomo Weiss},
  editor       = {John B. Carter and
                  Lixin Zhang},
  title        = {Selective main memory compression by identifying program phase changes},
  booktitle    = {Proceedings of the 3rd Workshop on Memory Performance Issues, in conjunction
                  with the 31st International Symposium on Computer Architecture 2004,
                  Munich, Germany, June 20, 2004},
  pages        = {96--101},
  publisher    = {{ACM}},
  year         = {2004},
  url          = {https://doi.org/10.1145/1054943.1054956},
  doi          = {10.1145/1054943.1054956},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/wmpi/NakarW04.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/wmpi/NatarajanCB04,
  author       = {Chitra Natarajan and
                  Bruce Christenson and
                  Faye A. Briggs},
  editor       = {John B. Carter and
                  Lixin Zhang},
  title        = {A study of performance impact of memory controller features in multi-processor
                  server environment},
  booktitle    = {Proceedings of the 3rd Workshop on Memory Performance Issues, in conjunction
                  with the 31st International Symposium on Computer Architecture 2004,
                  Munich, Germany, June 20, 2004},
  pages        = {80--87},
  publisher    = {{ACM}},
  year         = {2004},
  url          = {https://doi.org/10.1145/1054943.1054954},
  doi          = {10.1145/1054943.1054954},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/wmpi/NatarajanCB04.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/wmpi/PeriFK04,
  author       = {Ramesh V. Peri and
                  John Fernando and
                  Ravi K. Kolagotla},
  editor       = {John B. Carter and
                  Lixin Zhang},
  title        = {Addressing mode driven low power data caches for embedded processors},
  booktitle    = {Proceedings of the 3rd Workshop on Memory Performance Issues, in conjunction
                  with the 31st International Symposium on Computer Architecture 2004,
                  Munich, Germany, June 20, 2004},
  pages        = {129--135},
  publisher    = {{ACM}},
  year         = {2004},
  url          = {https://doi.org/10.1145/1054943.1054961},
  doi          = {10.1145/1054943.1054961},
  timestamp    = {Sat, 28 Aug 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/wmpi/PeriFK04.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/wmpi/RaabBR04,
  author       = {Wolfgang Raab and
                  Hans{-}Martin Bl{\"{u}}thgen and
                  Ulrich Ramacher},
  editor       = {John B. Carter and
                  Lixin Zhang},
  title        = {A low-power memory hierarchy for a fully programmable baseband processor},
  booktitle    = {Proceedings of the 3rd Workshop on Memory Performance Issues, in conjunction
                  with the 31st International Symposium on Computer Architecture 2004,
                  Munich, Germany, June 20, 2004},
  pages        = {102--106},
  publisher    = {{ACM}},
  year         = {2004},
  url          = {https://doi.org/10.1145/1054943.1054957},
  doi          = {10.1145/1054943.1054957},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/wmpi/RaabBR04.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/wmpi/SomogyiWHKAF04,
  author       = {Stephen Somogyi and
                  Thomas F. Wenisch and
                  Nikolaos Hardavellas and
                  Jangwoo Kim and
                  Anastassia Ailamaki and
                  Babak Falsafi},
  editor       = {John B. Carter and
                  Lixin Zhang},
  title        = {Memory coherence activity prediction in commercial workloads},
  booktitle    = {Proceedings of the 3rd Workshop on Memory Performance Issues, in conjunction
                  with the 31st International Symposium on Computer Architecture 2004,
                  Munich, Germany, June 20, 2004},
  pages        = {37--45},
  publisher    = {{ACM}},
  year         = {2004},
  url          = {https://doi.org/10.1145/1054943.1054949},
  doi          = {10.1145/1054943.1054949},
  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/wmpi/SomogyiWHKAF04.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/wmpi/SurendraBN04,
  author       = {G. Surendra and
                  Subhasis Banerjee and
                  S. K. Nandy},
  editor       = {John B. Carter and
                  Lixin Zhang},
  title        = {On the effectiveness of prefetching and reuse in reducing {L1} data
                  cache traffic: a case study of Snort},
  booktitle    = {Proceedings of the 3rd Workshop on Memory Performance Issues, in conjunction
                  with the 31st International Symposium on Computer Architecture 2004,
                  Munich, Germany, June 20, 2004},
  pages        = {88--95},
  publisher    = {{ACM}},
  year         = {2004},
  url          = {https://doi.org/10.1145/1054943.1054955},
  doi          = {10.1145/1054943.1054955},
  timestamp    = {Tue, 27 Apr 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/wmpi/SurendraBN04.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/wmpi/TakahashiKBTNS04,
  author       = {Chikafumi Takahashi and
                  Masaaki Kondo and
                  Taisuke Boku and
                  Daisuke Takahashi and
                  Hiroshi Nakamura and
                  Mitsuhisa Sato},
  editor       = {John B. Carter and
                  Lixin Zhang},
  title        = {{SCIMA-SMP:} on-chip memory processor architecture for {SMP}},
  booktitle    = {Proceedings of the 3rd Workshop on Memory Performance Issues, in conjunction
                  with the 31st International Symposium on Computer Architecture 2004,
                  Munich, Germany, June 20, 2004},
  pages        = {121--128},
  publisher    = {{ACM}},
  year         = {2004},
  url          = {https://doi.org/10.1145/1054943.1054960},
  doi          = {10.1145/1054943.1054960},
  timestamp    = {Fri, 22 Mar 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/wmpi/TakahashiKBTNS04.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/wmpi/WehmeyerHM04,
  author       = {Lars Wehmeyer and
                  Urs Helmig and
                  Peter Marwedel},
  editor       = {John B. Carter and
                  Lixin Zhang},
  title        = {Compiler-optimized usage of partitioned memories},
  booktitle    = {Proceedings of the 3rd Workshop on Memory Performance Issues, in conjunction
                  with the 31st International Symposium on Computer Architecture 2004,
                  Munich, Germany, June 20, 2004},
  pages        = {114--120},
  publisher    = {{ACM}},
  year         = {2004},
  url          = {https://doi.org/10.1145/1054943.1054959},
  doi          = {10.1145/1054943.1054959},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/wmpi/WehmeyerHM04.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/wmpi/2004,
  editor       = {John B. Carter and
                  Lixin Zhang},
  title        = {Proceedings of the 3rd Workshop on Memory Performance Issues, in conjunction
                  with the 31st International Symposium on Computer Architecture 2004,
                  Munich, Germany, June 20, 2004},
  publisher    = {{ACM}},
  year         = {2004},
  isbn         = {1-59593-040-X},
  timestamp    = {Tue, 26 Apr 2011 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/wmpi/2004.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}