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@inproceedings{DBLP:conf/vlsic/HashidaTOSSNTHS14,
  author       = {Takushi Hashida and
                  Yasumoto Tomita and
                  Yuuki Ogata and
                  Kosuke Suzuki and
                  Shigeto Suzuki and
                  Takanori Nakao and
                  Yuji Terao and
                  Satofumi Honda and
                  Sota Sakabayashi and
                  Ryuichi Nishiyama and
                  Akihiko Konmoto and
                  Yoshitomo Ozeki and
                  Hiroyuki Adachi and
                  Hisakatsu Yamaguchi and
                  Yoichi Koyanagi and
                  Hirotaka Tamura},
  title        = {A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm {CMOS} with 1-tap {DFE}
                  and quarter-rate clock distribution},
  booktitle    = {Symposium on {VLSI} Circuits, {VLSIC} 2014, Digest of Technical Papers,
                  Honolulu, HI, USA, June 10-13, 2014},
  pages        = {1--2},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/VLSIC.2014.6858359},
  doi          = {10.1109/VLSIC.2014.6858359},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsic/HashidaTOSSNTHS14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}